Author: Brendan Dahl Date: 2024-06-11T16:10:00-07:00 New Revision: 3ab6d126250f03982d3110517d407f7e951133f6
URL: https://github.com/llvm/llvm-project/commit/3ab6d126250f03982d3110517d407f7e951133f6 DIFF: https://github.com/llvm/llvm-project/commit/3ab6d126250f03982d3110517d407f7e951133f6.diff LOG: [WebAssembly] Implement f16x8 madd and nmadd instructions. (#95151) Implemented with intrinsics and builtins. Specified at: https://github.com/WebAssembly/half-precision/blob/main/proposals/half-precision/Overview.md Added: Modified: clang/include/clang/Basic/BuiltinsWebAssembly.def clang/lib/CodeGen/CGBuiltin.cpp clang/test/CodeGen/builtins-wasm.c llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td llvm/test/MC/WebAssembly/simd-encodings.s Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def index 4e48ff48b60f5..2a45f8a6582a2 100644 --- a/clang/include/clang/Basic/BuiltinsWebAssembly.def +++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def @@ -170,6 +170,8 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd") TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f16x8, "V8hV8hV8hV8h", "nc", "half-precision") +TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f16x8, "V8hV8hV8hV8h", "nc", "half-precision") TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd") TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 06e201fa71e6f..511e1fd4016d7 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -21149,6 +21149,8 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle); return Builder.CreateCall(Callee, Ops); } + case WebAssembly::BI__builtin_wasm_relaxed_madd_f16x8: + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f16x8: case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4: case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4: case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2: @@ -21158,10 +21160,12 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Value *C = EmitScalarExpr(E->getArg(2)); unsigned IntNo; switch (BuiltinID) { + case WebAssembly::BI__builtin_wasm_relaxed_madd_f16x8: case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4: case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2: IntNo = Intrinsic::wasm_relaxed_madd; break; + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f16x8: case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4: case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f64x2: IntNo = Intrinsic::wasm_relaxed_nmadd; diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index d6ee4f68700dc..75861b1b4bd6d 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -690,6 +690,20 @@ f64x2 nmadd_f64x2(f64x2 a, f64x2 b, f64x2 c) { // WEBASSEMBLY-NEXT: ret } +f16x8 madd_f16x8(f16x8 a, f16x8 b, f16x8 c) { + return __builtin_wasm_relaxed_madd_f16x8(a, b, c); + // WEBASSEMBLY: call <8 x half> @llvm.wasm.relaxed.madd.v8f16( + // WEBASSEMBLY-SAME: <8 x half> %a, <8 x half> %b, <8 x half> %c) + // WEBASSEMBLY-NEXT: ret +} + +f16x8 nmadd_f16x8(f16x8 a, f16x8 b, f16x8 c) { + return __builtin_wasm_relaxed_nmadd_f16x8(a, b, c); + // WEBASSEMBLY: call <8 x half> @llvm.wasm.relaxed.nmadd.v8f16( + // WEBASSEMBLY-SAME: <8 x half> %a, <8 x half> %b, <8 x half> %c) + // WEBASSEMBLY-NEXT: ret +} + i8x16 laneselect_i8x16(i8x16 a, i8x16 b, i8x16 c) { return __builtin_wasm_relaxed_laneselect_i8x16(a, b, c); // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8( diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 3c97befcea1a4..3888175efd115 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -1480,23 +1480,24 @@ defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero, // Relaxed (Negative) Multiply-Add (madd/nmadd) //===----------------------------------------------------------------------===// -multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS> { +multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS, list<Predicate> reqs> { defm MADD_#vec : - RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), - [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd - (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], - vec.prefix#".relaxed_madd\t$dst, $a, $b, $c", - vec.prefix#".relaxed_madd", simdopA>; + SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), + [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd + (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], + vec.prefix#".relaxed_madd\t$dst, $a, $b, $c", + vec.prefix#".relaxed_madd", simdopA, reqs>; defm NMADD_#vec : - RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), - [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd - (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], - vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c", - vec.prefix#".relaxed_nmadd", simdopS>; + SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), + [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd + (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], + vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c", + vec.prefix#".relaxed_nmadd", simdopS, reqs>; } -defm "" : SIMDMADD<F32x4, 0x105, 0x106>; -defm "" : SIMDMADD<F64x2, 0x107, 0x108>; +defm "" : SIMDMADD<F32x4, 0x105, 0x106, [HasRelaxedSIMD]>; +defm "" : SIMDMADD<F64x2, 0x107, 0x108, [HasRelaxedSIMD]>; +defm "" : SIMDMADD<F16x8, 0x146, 0x147, [HasHalfPrecision]>; //===----------------------------------------------------------------------===// // Laneselect diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s index 8e4d9301b6026..88c91be9263da 100644 --- a/llvm/test/MC/WebAssembly/simd-encodings.s +++ b/llvm/test/MC/WebAssembly/simd-encodings.s @@ -914,4 +914,10 @@ main: # CHECK: f16x8.nearest # encoding: [0xfd,0xbf,0x02] f16x8.nearest + # CHECK: f16x8.relaxed_madd # encoding: [0xfd,0xc6,0x02] + f16x8.relaxed_madd + + # CHECK: f16x8.relaxed_nmadd # encoding: [0xfd,0xc7,0x02] + f16x8.relaxed_nmadd + end_function _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
