llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Monad (YanWQ-monad) <details> <summary>Changes</summary> Specification: https://github.com/riscv/riscv-isa-manual/blob/main/src/smcdeleg.adoc `Ssccfg` introduces one new CSR `scountinhibit`. --- Full diff: https://github.com/llvm/llvm-project/pull/95163.diff 9 Files Affected: - (modified) clang/test/Preprocessor/riscv-target-features.c (+18) - (modified) llvm/docs/RISCVUsage.rst (+2) - (modified) llvm/docs/ReleaseNotes.rst (+1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7) - (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+5) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+8) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+6) - (modified) llvm/test/MC/RISCV/supervisor-csr-names.s (+18) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+2) ``````````diff diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 91307141e0406..576101b6ae50f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -27,9 +27,11 @@ // CHECK-NOT: __riscv_shvstvala {{.*$}} // CHECK-NOT: __riscv_shvstvecd {{.*$}} // CHECK-NOT: __riscv_smaia {{.*$}} +// CHECK-NOT: __riscv_smcdeleg {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} // CHECK-NOT: __riscv_smstateen {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_ssccfg {{.*$}} // CHECK-NOT: __riscv_ssccptr {{.*$}} // CHECK-NOT: __riscv_sscofpmf {{.*$}} // CHECK-NOT: __riscv_sscounterenw {{.*$}} @@ -362,6 +364,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVECD-EXT %s // CHECK-SHVSTVECD-EXT: __riscv_shvstvecd 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32issccfg -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCFG-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64issccfg -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCFG-EXT %s +// CHECK-SSCCFG-EXT: __riscv_ssccfg 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32issccptr -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCCPTR-EXT %s @@ -1393,6 +1403,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s // CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismcdeleg1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismcdeleg1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s +// CHECK-SMCDELEG-EXT: __riscv_smcdeleg 1000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32ismepmp1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index ef06f80c747f9..ffe93d7569a71 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -99,9 +99,11 @@ on support follow. ``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Smaia`` Supported + ``Smcdeleg`` Supported ``Smepmp`` Supported ``Smstateen`` Assembly Support ``Ssaia`` Supported + ``Ssccfg`` Supported ``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscofpmf`` Assembly Support ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 50c43fef3ad12..4efede4609481 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -157,6 +157,7 @@ Changes to the RISC-V Backend * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler. * Zabha is no longer experimental. * B (the collection of the Zba, Zbb, Zbs extensions) is supported. +* Added smcdeleg and ssccfg extensions to -march. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 011edca019fd6..ade2bf1608d33 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -859,6 +859,13 @@ def FeatureStdExtSmepmp : RISCVExtension<"smepmp", 1, 0, "'Smepmp' (Enhanced Physical Memory Protection)">; +def FeatureStdExtSmcdeleg + : RISCVExtension<"smcdeleg", 1, 0, + "'smcdeleg' (Counter Delegation Machine Level)">; +def FeatureStdExtSsccfg + : RISCVExtension<"ssccfg", 1, 0, + "'Ssccfg' (Counter Configuration Supervisor Level)">; + def FeatureStdExtSsccptr : RISCVExtension<"ssccptr", 1, 0, "'Ssccptr' (Main memory supports page table reads)">; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 01c2767119502..c717c0410a64b 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -310,6 +310,11 @@ foreach i = 3...31 in { def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; } +//===----------------------------------------------------------------------===// +// Supervisor Counter Setup +//===----------------------------------------------------------------------===// +def : SysReg<"scountinhibit", 0x120>; + //===----------------------------------------------------------------------===// // Debug/ Trace Registers (shared with Debug Mode) //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 86b557700347e..b1cf7198937fb 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -42,6 +42,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s ; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s ; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s +; RUN: llc -mtriple=riscv32 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCFG %s ; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s ; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s ; RUN: llc -mtriple=riscv32 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOUNTERENW %s @@ -111,6 +112,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s +; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s @@ -170,6 +172,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s ; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s ; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s +; RUN: llc -mtriple=riscv64 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCFG %s ; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s ; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s ; RUN: llc -mtriple=riscv64 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOUNTERENW %s @@ -245,6 +248,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s +; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s @@ -316,6 +320,7 @@ ; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0" ; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0" ; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0" +; RV32SSCCFG: .attribute 5, "rv32i2p1_ssccfg1p0" ; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0" ; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0" ; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0" @@ -385,6 +390,7 @@ ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0" ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" +; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" @@ -447,6 +453,7 @@ ; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0" ; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0" ; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0" +; RV64SSCCFG: .attribute 5, "rv64i2p1_ssccfg1p0" ; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0" ; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0" ; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0" @@ -518,6 +525,7 @@ ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" +; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 0e5eddd83e408..7f8ca6274122f 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -315,9 +315,15 @@ .attribute arch, "rv32i_ssaia1p0" # CHECK: attribute 5, "rv32i2p1_ssaia1p0" +.attribute arch, "rv32i_smcdeleg1p0" +# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0" + .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_ssccfg1p0" +# CHECK: attribute 5, "rv32i2p1_ssccfg1p0" + .attribute arch, "rv32i_ssccptr1p0" # CHECK: attribute 5, "rv32i2p1_ssccptr1p0" diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s index 127812de4bdc9..1f995c6114dd8 100644 --- a/llvm/test/MC/RISCV/supervisor-csr-names.s +++ b/llvm/test/MC/RISCV/supervisor-csr-names.s @@ -369,3 +369,21 @@ csrrs t2, 0x15C, zero csrrs t1, stopi, zero # uimm12 csrrs t2, 0xDB0, zero + +######################################### +# Counter Configuration (Ssccfg) +######################################### + +# scountinhibit +# name +# CHECK-INST: csrrs t1, scountinhibit, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x12] +# CHECK-INST-ALIAS: csrr t1, scountinhibit +# uimm12 +# CHECK-INST: csrrs t2, scountinhibit, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x12] +# CHECK-INST-ALIAS: csrr t2, scountinhibit +# name +csrrs t1, scountinhibit, zero +# uimm12 +csrrs t2, 0x120, zero diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 128321fc3ae73..a915c8a810280 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1009,9 +1009,11 @@ R"(All available -march extensions for RISC-V shvstvala 1.0 shvstvecd 1.0 smaia 1.0 + smcdeleg 1.0 smepmp 1.0 smstateen 1.0 ssaia 1.0 + ssccfg 1.0 ssccptr 1.0 sscofpmf 1.0 sscounterenw 1.0 `````````` </details> https://github.com/llvm/llvm-project/pull/95163 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
