[clang] [llvm] [AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Vikram Hegde via cfe-commits]

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@@ -5456,43 +5444,32 @@ bool 
AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
   if ((Size % 32) == 0) {
     SmallVector<Register, 2> PartialRes;
     unsigned NumParts = Size / 32;
-    auto IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
+    bool IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
----------------
vikramRH wrote:

done

https://github.com/llvm/llvm-project/pull/89217
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