Author: Pavel Iliin Date: 2024-05-03T00:58:17+01:00 New Revision: ff210b94d449de8ebe1f32cf0d7763ba63b27b39
URL: https://github.com/llvm/llvm-project/commit/ff210b94d449de8ebe1f32cf0d7763ba63b27b39 DIFF: https://github.com/llvm/llvm-project/commit/ff210b94d449de8ebe1f32cf0d7763ba63b27b39.diff LOG: [FMV][NFC] Add test for bti and mte check in resolver. Added: Modified: clang/test/CodeGen/attr-target-clones-aarch64.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c b/clang/test/CodeGen/attr-target-clones-aarch64.c index 8c8b951e9118d7..f75d8a69ebf02f 100644 --- a/clang/test/CodeGen/attr-target-clones-aarch64.c +++ b/clang/test/CodeGen/attr-target-clones-aarch64.c @@ -1,13 +1,15 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals --include-generated-funcs // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +mte -target-feature +bti -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-MTE-BTI int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; } int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; } int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; } int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; } +int __attribute__((target_clones("memtag2", "bti"))) ftc_dup3(void) { return 4; } int foo() { - return ftc() + ftc_def() + ftc_dup1() + ftc_dup2(); + return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3(); } inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; } @@ -29,6 +31,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK: @ftc_def.ifunc = weak_odr alias i32 (), ptr @ftc_def // CHECK: @ftc_dup1.ifunc = weak_odr alias i32 (), ptr @ftc_dup1 // CHECK: @ftc_dup2.ifunc = weak_odr alias i32 (), ptr @ftc_dup2 +// CHECK: @ftc_dup3.ifunc = weak_odr alias i32 (), ptr @ftc_dup3 // CHECK: @ftc_inline2.ifunc = weak_odr alias i32 (), ptr @ftc_inline2 // CHECK: @ftc_inline1.ifunc = weak_odr alias i32 (), ptr @ftc_inline1 // CHECK: @ftc_inline3.ifunc = weak_odr alias i32 (), ptr @ftc_inline3 @@ -36,10 +39,29 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver // CHECK: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver // CHECK: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver +// CHECK: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver // CHECK: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver // CHECK: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver // CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver //. +// CHECK-MTE-BTI: @__aarch64_cpu_features = external dso_local global { i64 } +// CHECK-MTE-BTI: @ftc.ifunc = weak_odr alias i32 (), ptr @ftc +// CHECK-MTE-BTI: @ftc_def.ifunc = weak_odr alias i32 (), ptr @ftc_def +// CHECK-MTE-BTI: @ftc_dup1.ifunc = weak_odr alias i32 (), ptr @ftc_dup1 +// CHECK-MTE-BTI: @ftc_dup2.ifunc = weak_odr alias i32 (), ptr @ftc_dup2 +// CHECK-MTE-BTI: @ftc_dup3.ifunc = weak_odr alias i32 (), ptr @ftc_dup3 +// CHECK-MTE-BTI: @ftc_inline2.ifunc = weak_odr alias i32 (), ptr @ftc_inline2 +// CHECK-MTE-BTI: @ftc_inline1.ifunc = weak_odr alias i32 (), ptr @ftc_inline1 +// CHECK-MTE-BTI: @ftc_inline3.ifunc = weak_odr alias i32 (), ptr @ftc_inline3 +// CHECK-MTE-BTI: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver +// CHECK-MTE-BTI: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver +// CHECK-MTE-BTI: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver +// CHECK-MTE-BTI: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver +// CHECK-MTE-BTI: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver +// CHECK-MTE-BTI: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver +// CHECK-MTE-BTI: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver +// CHECK-MTE-BTI: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver +//. // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: @ftc._MaesMlse( // CHECK-NEXT: entry: @@ -155,6 +177,40 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // // CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: @ftc_dup3._Mmemtag2( +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: @ftc_dup3._Mbti( +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 +// +// +// CHECK-LABEL: @ftc_dup3.resolver( +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @ftc_dup3._Mbti +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag2 +// CHECK: resolver_else2: +// CHECK-NEXT: ret ptr @ftc_dup3.default +// +// +// CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: @foo( // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc() @@ -164,7 +220,9 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] // CHECK-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] -// CHECK-NEXT: ret i32 [[ADD5]] +// CHECK-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-NEXT: ret i32 [[ADD7]] // // // CHECK: Function Attrs: noinline nounwind optnone @@ -299,6 +357,12 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // // CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: @ftc_dup3.default( +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 +// +// +// CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: @ftc_inline2.default( // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 @@ -371,6 +435,12 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // // CHECK-NOFMV: Function Attrs: noinline nounwind optnone +// CHECK-NOFMV-LABEL: @ftc_dup3( +// CHECK-NOFMV-NEXT: entry: +// CHECK-NOFMV-NEXT: ret i32 4 +// +// +// CHECK-NOFMV: Function Attrs: noinline nounwind optnone // CHECK-NOFMV-LABEL: @foo( // CHECK-NOFMV-NEXT: entry: // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @ftc() @@ -380,7 +450,9 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] // CHECK-NOFMV-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] -// CHECK-NOFMV-NEXT: ret i32 [[ADD5]] +// CHECK-NOFMV-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() +// CHECK-NOFMV-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-NOFMV-NEXT: ret i32 [[ADD7]] // // // CHECK-NOFMV: Function Attrs: noinline nounwind optnone @@ -403,6 +475,329 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] // CHECK-NOFMV-NEXT: ret i32 [[ADD5]] // +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc._MaesMlse( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 0 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc._Msve2( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 0 +// +// +// CHECK-MTE-BTI-LABEL: @ftc.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2 +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc.default +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_def._Msha2( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_def._Mmemtag2Msha2( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI-LABEL: @ftc_def.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Mmemtag2Msha2 +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Msha2 +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def.default +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup1._Msha2( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 +// +// +// CHECK-MTE-BTI-LABEL: @ftc_dup1.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1._Msha2 +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1.default +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup2._Mfp( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup2._McrcMdotprod( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// +// +// CHECK-MTE-BTI-LABEL: @ftc_dup2.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1040 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1040 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._McrcMdotprod +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._Mfp +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup3._Mmemtag2( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 4 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup3._Mbti( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 4 +// +// +// CHECK-MTE-BTI-LABEL: @ftc_dup3.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mbti +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @foo( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: [[CALL:%.*]] = call i32 @ftc() +// CHECK-MTE-BTI-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() +// CHECK-MTE-BTI-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-MTE-BTI-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1() +// CHECK-MTE-BTI-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-MTE-BTI-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() +// CHECK-MTE-BTI-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] +// CHECK-MTE-BTI-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() +// CHECK-MTE-BTI-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-MTE-BTI-NEXT: ret i32 [[ADD7]] +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline2._Mfp16( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_direct( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 4 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @main( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK-MTE-BTI-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-MTE-BTI-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1() +// CHECK-MTE-BTI-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2() +// CHECK-MTE-BTI-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-MTE-BTI-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3() +// CHECK-MTE-BTI-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-MTE-BTI-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() +// CHECK-MTE-BTI-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] +// CHECK-MTE-BTI-NEXT: ret i32 [[ADD5]] +// +// +// CHECK-MTE-BTI-LABEL: @ftc_inline1.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._MpredresMrcpc +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513 +// CHECK-MTE-BTI-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 513 +// CHECK-MTE-BTI-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] +// CHECK-MTE-BTI: resolver_return3: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._MrngMsimd +// CHECK-MTE-BTI: resolver_else4: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1.default +// +// +// CHECK-MTE-BTI-LABEL: @ftc_inline2.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65536 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2._Mfp16 +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2.default +// +// +// CHECK-MTE-BTI-LABEL: @ftc_inline3.resolver( +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline2._MfcmaMsve2-bitperm( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 0 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_def.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup1.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup2.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_dup3.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 4 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline2.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline1._MrngMsimd( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline1._MpredresMrcpc( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline1._Msve2-aesMwfxt( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline1.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline3._Mbti( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline3._MsbMsve( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// +// +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: @ftc_inline3.default( +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 +// //. // CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" } // CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" } @@ -410,21 +805,38 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" } // CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" } // CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" } -// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" } -// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" } -// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" } -// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" } -// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" } -// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" } -// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" } +// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mte" } +// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" } +// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" } +// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" } +// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" } +// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" } +// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" } +// CHECK: attributes #[[ATTR14:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" } //. // CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } // CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } //. +// CHECK-MTE-BTI: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+lse,+mte,+neon" } +// CHECK-MTE-BTI: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2" } +// CHECK-MTE-BTI: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+sha2" } +// CHECK-MTE-BTI: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon" } +// CHECK-MTE-BTI: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+crc,+dotprod,+fp-armv8,+mte,+neon" } +// CHECK-MTE-BTI: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte" } +// CHECK-MTE-BTI: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon" } +// CHECK-MTE-BTI: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+complxnum,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-bitperm" } +// CHECK-MTE-BTI: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+rand" } +// CHECK-MTE-BTI: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte,+predres,+rcpc" } +// CHECK-MTE-BTI: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-aes,+wfxt" } +// CHECK-MTE-BTI: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sb,+sve" } +//. // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} //. // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} //. +// CHECK-MTE-BTI: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK-MTE-BTI: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. 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