================
@@ -447,6 +447,16 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2",
"ARMProcFamily", "NeoverseN2
FeatureEnableSelectOptimize,
FeaturePredictableSelectIsExpensive]>;
+def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily",
"NeoverseN3",
+ "Neoverse N3 ARM processors", [
+ FeatureFuseAES,
+ FeaturePostRAScheduler,
+ FeatureCmpBccFusion,
----------------
davemgreen wrote:
Hi - Should FeatureCmpBccFusion be enabled over what is in N2? The core might
well be able to fuse them, but I don't think that is new and from what I
remember the performance was sometimes worse with it enabled. (I think llvm's
implementation of FeatureCmpBccFusion might be a bit more aggressive than is
helpful).
https://github.com/llvm/llvm-project/pull/90143
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