https://github.com/Khao7342 updated https://github.com/llvm/llvm-project/pull/89359
>From e51498e67409836b099fa892b17d71e44a7d403b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=83=9D=E5=BA=B7=E8=BE=BE?= <haokan...@bosc.ac.cn> Date: Fri, 19 Apr 2024 17:18:10 +0800 Subject: [PATCH] [RISCV] Add processor definition for XiangShan-KunMingHu This pull request adds definitions for the XiangShan-KunMingHu processor. "XiangShan" is a high-performance open-source RISC-V processor project, and "KunMingHu" architecture is its third generation. Official documentation can be found at: [documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/). Currently, the KunMingHu core supports"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei". The scheduler model and other components will be submitted in subsequent patches. Co-Authored-By: Bhe6669 <167076958+bhe6...@users.noreply.github.com> Co-Authored-By: huxuan0307 <39661208+huxuan0...@users.noreply.github.com> --- clang/test/Driver/riscv-cpus.c | 36 +++++++++++++++++++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 +-- llvm/lib/Target/RISCV/RISCVProcessors.td | 27 +++++++++++++++++ 3 files changed, 65 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..be13c17df04742 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -31,6 +31,39 @@ // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval" // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s +// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zifencei" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknd" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkne" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknh" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32f" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32x" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl32b" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl64b" +// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d" + // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s @@ -76,6 +109,9 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-kunminghu | FileCheck -check-prefix=MTUNE-XIANGSHAN-KUNMINGHU %s +// MTUNE-XIANGSHAN-KUNMINGHU: "-tune-cpu" "xiangshan-kunminghu" + // Check mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s // MTUNE-GENERIC-32: "-tune-cpu" "generic" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 9c91c4157cd6a0..349785fed7dc72 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-kunminghu, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-kunminghu, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index f9a557e02bfe1a..14a83ac2e3af5f 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -378,3 +378,30 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZkn, + FeatureStdExtZksed, + FeatureStdExtZksh, + FeatureStdExtSvinval, + FeatureStdExtZicbom, + FeatureStdExtZicboz, + FeatureStdExtV, + FeatureStdExtZvl128b], + [TuneNoDefaultUnroll, + TuneZExtHFusion, + TuneZExtWFusion, + TuneShiftedZExtWFusion]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
