arsenm wrote:

> Some of the GPU targets, IIRC, want daz/ftz by default. Not all targets have 
> DAZ/FTZ bits that can be set; I think RISC-V is in this category, although to 
> be honest, trying to track down all the ISA extensions to make sure is a bit 
> beyond my ken.
> 
OpenCL allows you to flush float denorms by default and has an explicit flag 
for it, which is allowed to only change the f32 mode. For AMDGPU we default to 
no denormals on old targets without fast support. This is also somewhat forced 
because unfortunately OpenCL only provided a flag to enable flushing and not go 
in the other direction.

> It's a real mess since some targets flush to positive zero and some targets 
> flush to signed zero and some manuals I couldn't make heads or tails out of 
> what they actually did.

I believe ARM has a control bit to set if you want the flush to positive zero 
or preserve sign mode. I don't see why anyone would ever want the positive zero 
mode. I'm not sure there are any other users 

https://github.com/llvm/llvm-project/pull/89477
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