https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/82809
>From 557e7163d744890aadfa703a81a0c4f2cd112517 Mon Sep 17 00:00:00 2001
From: zhijian <zhij...@ca.ibm.com>
Date: Fri, 23 Feb 2024 13:23:18 -0500
Subject: [PATCH 1/6] Implement a subset of builtin_cpu_supports() features
---
clang/lib/Basic/Targets/PPC.cpp | 15 +-
clang/lib/Basic/Targets/PPC.h | 9 +-
clang/lib/CodeGen/CGBuiltin.cpp | 104 +++++++++++---
clang/lib/Sema/SemaChecking.cpp | 6 +-
clang/test/CodeGen/aix-builtin-cpu-is.c | 4 +-
clang/test/CodeGen/aix-builtin-cpu-supports.c | 135 ++++++++++++++++++
clang/test/Sema/aix-builtin-cpu-unsupports.c | 40 +++++-
.../test/Sema/builtin-cpu-unsupports-AIX-Os.c | 9 ++
.../llvm/TargetParser/PPCTargetParser.def | 73 +++++++++-
9 files changed, 356 insertions(+), 39 deletions(-)
create mode 100644 clang/test/CodeGen/aix-builtin-cpu-supports.c
create mode 100644 clang/test/Sema/builtin-cpu-unsupports-AIX-Os.c
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index aebe51bfa4daad..1d488dff825ede 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -897,6 +897,19 @@ ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins()
const {
}
bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+ llvm::Triple Triple = getTriple();
+ if (Triple.isOSAIX()) {
+#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP,
\
+ VALUE)
\
+ .Case(NAME, true)
+ return llvm::StringSwitch<bool>(FeatureStr)
+#include "llvm/TargetParser/PPCTargetParser.def"
+ .Default(false);
+ }
+
+ assert(Triple.isOSLinux() &&
+ "__builtin_cpu_supports() is only supported for AIX and Linux.");
+
#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME,
true)
return llvm::StringSwitch<bool>(FeatureStr)
#include "llvm/TargetParser/PPCTargetParser.def"
@@ -906,7 +919,7 @@ bool PPCTargetInfo::validateCpuSupports(StringRef
FeatureStr) const {
bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
llvm::Triple Triple = getTriple();
if (Triple.isOSAIX()) {
-#define PPC_AIX_CPU(NAME, SUPPORT, INDEX, OP, VALUE) .Case(NAME, true)
+#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, OP, VALUE) .Case(NAME, true)
return llvm::StringSwitch<bool>(CPUName)
#include "llvm/TargetParser/PPCTargetParser.def"
.Default(false);
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 70683916a8b04f..39b52d362f36b8 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCpuSupports() const override { return getTriple().isOSGlibc(); }
+ bool supportsCpuSupports() const override {
+ llvm::Triple Triple = getTriple();
+ // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports().
+ return Triple.isOSGlibc() ||
+ (Triple.isOSAIX() &&
+ !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
+ }
+
bool supportsCpuIs() const override {
llvm::Triple Triple = getTriple();
// AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 9ee51ca7142c77..1565e4103d9ef8 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16570,7 +16570,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+ unsigned Mask, unsigned CompOp,
unsigned OpValue) -> Value * {
if (SupportMethod == AIX_BUILTIN_PPC_FALSE)
return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
@@ -16578,24 +16578,64 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
if (SupportMethod == AIX_BUILTIN_PPC_TRUE)
return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
- assert(SupportMethod <= USE_SYS_CONF && "Invalid value for
SupportMethod.");
- assert((CompOp == COMP_EQ) && "Only equal comparisons are supported.");
+ assert(SupportMethod <= SYS_CALL && "Invalid value for SupportMethod.");
+
+ llvm::Value *FieldValue = nullptr;
+ if (SupportMethod == USE_SYS_CONF) {
+ llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+ llvm::Constant *SysConf =
+ CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+ // Grab the appropriate field from _system_configuration.
+ llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+ ConstantInt::get(Int32Ty, FieldIdx)};
+
+ FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+ FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+ CharUnits::fromQuantity(4));
+ } else if (SupportMethod == SYS_CALL) {
+ llvm::FunctionType *FTy =
+ llvm::FunctionType::get(Int64Ty, Int32Ty, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "getsystemcfg");
+
+ FieldValue =
+ Builder.CreateCall(Func, {ConstantInt::get(Int32Ty, FieldIdx)});
+ }
+ assert((FieldValue != nullptr) &&
+ "SupportMethod value is not defined in PPCTargetParser.def.");
+
+ if (Mask)
+ FieldValue = Builder.CreateAnd(FieldValue, Mask);
- llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
- llvm::Constant *SysConf =
- CGM.CreateRuntimeVariable(STy, "_system_configuration");
+ CmpInst::Predicate PreOp;
+ switch (CompOp) {
+ case COMP_EQ:
+ PreOp = ICmpInst::ICMP_EQ;
+ break;
+ case COMP_GT:
+ PreOp = ICmpInst::ICMP_UGT;
+ break;
+ case COMP_GE:
+ PreOp = ICmpInst::ICMP_UGE;
+ break;
+ case COMP_NE:
+ PreOp = ICmpInst::ICMP_NE;
+ break;
+ default:
+ llvm_unreachable(
+ "Compare type does not match types defined in PPCTargetParser.def!");
+ }
- // Grab the appropriate field from _system_configuration.
- llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
- ConstantInt::get(Int32Ty, FieldIdx)};
+ llvm::Type *ValueType = FieldValue->getType();
+ bool IsValueType64Bit = ValueType->isIntegerTy(64);
+ assert(
+ (IsValueType64Bit || ValueType->isIntegerTy(32)) &&
+ "Only 32/64-bit integers are supported in GenAIXPPCBuiltinCpuExpr().");
- llvm::Value *FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
- FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
- CharUnits::fromQuantity(4));
- assert(FieldValue->getType()->isIntegerTy(32) &&
- "Only 32-bit integers are supported in GenAIXPPCBuiltinCpuExpr().");
- return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
- ConstantInt::get(Int32Ty, OpValue));
+ return Builder.CreateICmp(
+ PreOp, FieldValue,
+ ConstantInt::get(IsValueType64Bit ? Int64Ty : Int32Ty, OpValue));
};
switch (BuiltinID) {
@@ -16607,15 +16647,15 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
llvm::Triple Triple = getTarget().getTriple();
if (Triple.isOSAIX()) {
- unsigned IsCpuSupport, FieldIdx, CompareOp, CpuIdValue;
+ unsigned SupportMethod, FieldIdx, CompareOp, CpuIdValue;
typedef std::tuple<unsigned, unsigned, unsigned, unsigned> CPUType;
- std::tie(IsCpuSupport, FieldIdx, CompareOp, CpuIdValue) =
+ std::tie(SupportMethod, FieldIdx, CompareOp, CpuIdValue) =
static_cast<CPUType>(StringSwitch<CPUType>(CPUStr)
-#define PPC_AIX_CPU(NAME, SUPPORT_MAGIC, INDEX, COMPARE_OP, VALUE)
\
- .Case(NAME, {SUPPORT_MAGIC, INDEX, COMPARE_OP, VALUE})
+#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
\
+ .Case(NAME, {SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE})
#include "llvm/TargetParser/PPCTargetParser.def"
);
- return GenAIXPPCBuiltinCpuExpr(IsCpuSupport, FieldIdx, CompareOp,
+ return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, 0, CompareOp,
CpuIdValue);
}
@@ -16633,10 +16673,28 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
llvm::ConstantInt::get(Int32Ty, NumCPUID));
}
case Builtin::BI__builtin_cpu_supports: {
- unsigned FeatureWord;
- unsigned BitMask;
+ llvm::Triple Triple = getTarget().getTriple();
const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
+ if (Triple.isOSAIX()) {
+ unsigned SupportMethod, FieldIdx, Mask, CompOp, Value;
+ typedef std::tuple<unsigned, unsigned, unsigned, unsigned, unsigned>
+ CPUSupportType;
+ std::tie(SupportMethod, FieldIdx, Mask, CompOp, Value) =
+ static_cast<CPUSupportType>(StringSwitch<CPUSupportType>(CPUStr)
+#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP,
\
+ VALUE)
\
+ .Case(NAME, {SUPPORT_METHOD, INDEX, MASK, COMP_OP, VALUE})
+#include "llvm/TargetParser/PPCTargetParser.def"
+ );
+ return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, Mask, CompOp,
+ Value);
+ }
+
+ assert(Triple.isOSLinux() &&
+ "__builtin_cpu_supports() is only supported for AIX and Linux.");
+ unsigned FeatureWord;
+ unsigned BitMask;
std::tie(FeatureWord, BitMask) =
StringSwitch<std::pair<unsigned, unsigned>>(CPUStr)
#define PPC_LNX_FEATURE(Name, Description, EnumName, Bitmask, FA_WORD)
\
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 2cda1d08784ece..6071cb7655b724 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2162,10 +2162,8 @@ static bool SemaBuiltinCpu(Sema &S, const TargetInfo
&TI, CallExpr *TheCall,
if (!SupportsBI(&TI) && SupportsBI(AuxTI))
TheTI = AuxTI;
- if (IsCPUSupports && !TheTI->supportsCpuSupports())
- return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
- << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
- if (!IsCPUSupports && !TheTI->supportsCpuIs())
+ if ((!IsCPUSupports && !TheTI->supportsCpuIs()) ||
+ (IsCPUSupports && !TheTI->supportsCpuSupports()))
return S.Diag(TheCall->getBeginLoc(),
TI.getTriple().isOSAIX()
? diag::err_builtin_aix_os_unsupported
diff --git a/clang/test/CodeGen/aix-builtin-cpu-is.c
b/clang/test/CodeGen/aix-builtin-cpu-is.c
index b0a0dec41b56c0..e17cf7353511a2 100644
--- a/clang/test/CodeGen/aix-builtin-cpu-is.c
+++ b/clang/test/CodeGen/aix-builtin-cpu-is.c
@@ -57,12 +57,12 @@
// CHECK-NEXT: ret i32 0
// CHECK-NEXT: }
-// CHECKOP: @_system_configuration = external global { i32, i32, i32 }
+// CHECKOP: @_system_configuration = external global { i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32,
i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8, i8,
i8, i32, i32, i16, i16, [3 x i32], i32 }
// CHECKOP: define i32 @main() #0 {
// CHECKOP-NEXT: entry:
// CHECKOP-NEXT: %retval = alloca i32, align 4
// CHECKOP-NEXT: store i32 0, ptr %retval, align 4
-// CHECKOP-NEXT: %0 = load i32, ptr getelementptr inbounds ({ i32, i32, i32
}, ptr @_system_configuration, i32 0, i32 1), align 4
+// CHECKOP-NEXT: %0 = load i32, ptr getelementptr inbounds ({ i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32,
i32, i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8,
i8, i8, i32, i32, i16, i16, [3 x i32], i32 }, ptr @_system_configuration, i32
0, i32 1), align 4
// CHECKOP-NEXT: %1 = icmp eq i32 %0, [[VALUE]]
// CHECKOP-NEXT: %conv = zext i1 %1 to i32
// CHECKOP-NEXT: ret i32 %conv
diff --git a/clang/test/CodeGen/aix-builtin-cpu-supports.c
b/clang/test/CodeGen/aix-builtin-cpu-supports.c
new file mode 100644
index 00000000000000..db144fd318f7b2
--- /dev/null
+++ b/clang/test/CodeGen/aix-builtin-cpu-supports.c
@@ -0,0 +1,135 @@
+// RUN: echo "int main() { return __builtin_cpu_supports(\"4xxmac\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"altivec\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=46 -DOP=ugt -DBIT=i32 -DVALUE=0 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"booke\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"cellbe\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"darn\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=262144 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"efpdouble\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"efpsingle\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"pa6t\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"fpu\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"htm\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=ugt -DLABLE=59 -DBIT=i64 -DVALUE=0 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCALL
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"mma\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=ugt -DLABLE=62 -DBIT=i64 -DVALUE=0 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCALL
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"mmu\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_2_05\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_2_06\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=32768 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_2_07\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=65536 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_3_00\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=131072 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_3_1\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=262144 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"dfp\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=53 -DOP=ne -DBIT=i32 -DVALUE=0 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"power4\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"power5\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"power5+\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"power6x\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ppc32\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ppc601\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ppc64\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ppcle\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"smt\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=44 -DMASK=3 -DOP=eq -DBIT=i32 -DVALUE=3 \
+// RUN: --check-prefixes=CHECKOP,OPMASK,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"spe\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"true_le\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ucache\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=5 -DMASK=2 -DOP=eq -DBIT=i32 -DVALUE=2 \
+// RUN: --check-prefixes=CHECKOP,OPMASK,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"vsx\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=46 -DOP=ugt -DBIT=i32 -DVALUE=1 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// CHECK: define i32 @main() #0 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: %retval = alloca i32, align 4
+// CHECK-NEXT: store i32 0, ptr %retval, align 4
+// CHECK-NEXT: ret i32 [[BOOL]]
+// CHECK-NEXT: }
+
+// SYSCONF: @_system_configuration = external global { i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32,
i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8, i8,
i8, i32, i32, i16, i16, [3 x i32], i32 }
+
+// CHECKOP: define i32 @main() #0 {
+// CHECKOP-NEXT: entry:
+// CHECKOP-NEXT: %retval = alloca i32, align 4
+// CHECKOP-NEXT: store i32 0, ptr %retval, align 4
+
+// SYSCONF-NEXT: %0 = load i32, ptr getelementptr inbounds ({ i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32,
i32, i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8,
i8, i8, i32, i32, i16, i16, [3 x i32], i32 }, ptr @_system_configuration, i32
0, i32 [[POS]]), align 4
+// SYSCALL-NEXT: %0 = call i64 @getsystemcfg(i32 [[LABLE]])
+
+// OPRT-NEXT: %1 = icmp [[OP]] [[BIT]] %0, [[VALUE]]
+// OPRT-NEXT: %conv = zext i1 %1 to i32
+
+// OPMASK-NEXT: %1 = and i32 %0, [[MASK]]
+// OPMASK-NEXT: %2 = icmp [[OP]] i32 %1, [[VALUE]]
+// OPMASK-NEXT: %conv = zext i1 %2 to i32
+
+// CHECKOP-NEXT: ret i32 %conv
+// CHECKOP-NEXT: }
+
+// SYSCALL: declare i64 @getsystemcfg(i32)
+
+
diff --git a/clang/test/Sema/aix-builtin-cpu-unsupports.c
b/clang/test/Sema/aix-builtin-cpu-unsupports.c
index 10e21867c39373..39cf3aea747f6e 100644
--- a/clang/test/Sema/aix-builtin-cpu-unsupports.c
+++ b/clang/test/Sema/aix-builtin-cpu-unsupports.c
@@ -1,6 +1,42 @@
-// RUN: %clang_cc1 -fsyntax-only -triple powerpc-ibm-aix7.1.0.0 -verify %s
+// RUN: %clang_cc1 -fsyntax-only -triple powerpc-ibm-aix7.2.0.0 -verify %s
int main(void) {
- if (__builtin_cpu_is("power8")) // expected-error {{this builtin is
available only on AIX 7.2 and later operating systems}}
+ if (__builtin_cpu_supports("aes")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("archpmu")) // expected-error {{invalid cpu
feature string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("dscr")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("ebb")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("htm-nosc")) // expected-error {{invalid cpu
feature string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("htm-no-suspend")) // expected-error {{invalid
cpu feature string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("ic_snoop")) // expected-error {{invalid cpu
feature string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("ieee128")) // expected-error {{invalid cpu
feature string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("isel")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("notb")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("scv")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("tar")) // expected-error {{invalid cpu feature
string for builtin}}
+ return 1;
+
+ if (__builtin_cpu_supports("vcrypto")) // expected-error {{invalid cpu
feature string for builtin}}
return 1;
}
diff --git a/clang/test/Sema/builtin-cpu-unsupports-AIX-Os.c
b/clang/test/Sema/builtin-cpu-unsupports-AIX-Os.c
new file mode 100644
index 00000000000000..25d25b2ac4c924
--- /dev/null
+++ b/clang/test/Sema/builtin-cpu-unsupports-AIX-Os.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -fsyntax-only -triple powerpc-ibm-aix7.1.0.0 -verify %s
+
+int main(void) {
+ if (__builtin_cpu_is("power8")) // expected-error {{this builtin is
available only on AIX 7.2 and later operating systems}}
+ return 1;
+
+ if (__builtin_cpu_supports("power8")) // expected-error {{this builtin is
available only on AIX 7.2 and later operating systems}}
+ return 1;
+}
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index 88c7304659c4d9..bae4baf8422609 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -132,6 +132,14 @@ PPC_LNX_CPU("power10",47)
#ifndef AIX_POWERPC_USE_SYS_CONF
#define AIX_POWERPC_USE_SYS_CONF
#define AIX_SYSCON_IMPL_IDX 1
+ #define AIX_SYSCON_CACHE_IDX 5
+ #define AIX_SYSCON_SMT_IDX 44
+ #define AIX_SYSCON_VMX_IDX 46
+ #define AIX_SYSCON_DFP_IDX 53
+
+ #define SYS_CALL_TM_VER 59
+ #define SYS_CALL_MMA_VER 62
+
#define AIX_PPC7_VALUE 0x00008000
#define AIX_PPC8_VALUE 0x00010000
#define AIX_PPC9_VALUE 0x00020000
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP_NE 3
#endif
// The value of SUPPORT_METHOD can be AIX_BUILTIN_PPC_TRUE,
-// AIX_BUILTIN_PPC_FALSE, or USE_SYS_CONF.
-// When the value of SUPPORT_METHOD is USE_SYS_CONF, the return value
-// depends on the result of comparing the data member of
-// _system_configuration specified by INDEX with a certain value.
+// AIX_BUILTIN_PPC_FALSE, USE_SYS_CONF, SYS_CALL.
+// When the value of SUPPORT_METHOD is set to USE_SYS_CONF, the return value
+// depends on comparing VALUE with the specified data member of
+// _system_configuration at INDEX, where the data member is masked by Mask.
+// When the SUPPORT_METHOD value is set to SYS_CALL, the return value depends
+// on comparing a VALUE with the return value of calling `getsystemcfg`
+// with the parameter INDEX, which is then masked by Mask.
#ifndef PPC_AIX_CPU
#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
#endif
-// __builtin_cpu_is() is supported only on Power7 and up.
+// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on
Power7 and up.
PPC_AIX_CPU("power4",AIX_BUILTIN_PPC_FALSE,0,0,0)
PPC_AIX_CPU("ppc970",AIX_BUILTIN_PPC_FALSE,0,0,0)
PPC_AIX_CPU("power5",AIX_BUILTIN_PPC_FALSE,0,0,0)
@@ -176,11 +191,57 @@
PPC_AIX_CPU("power9",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC9_VALUE)
PPC_AIX_CPU("power10",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC10_VALUE)
#undef PPC_AIX_CPU
+#ifndef PPC_AIX_FEATURE
+#define PPC_AIX_FEATURE(NAME,DESC,SUPPORT_METHOD,INDEX,MASK,COMPARE_OP,VALUE)
+#endif
+
+PPC_AIX_FEATURE("4xxmac","4xx CPU has a Multiply
Accumulator",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector
Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,COMP_GT,0)
+PPC_AIX_FEATURE("arch_2_05","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("arch_2_06","CPU supports ISA 206 (eg,
POWER7)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC7_VALUE)
+PPC_AIX_FEATURE("arch_2_07","CPU supports ISA 207 (eg,
POWER8)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC9_VALUE)
+PPC_AIX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA
category",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband
engine",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number)
instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("dfp","CPU has a decimal floating point
unit",USE_SYS_CONF,AIX_SYSCON_DFP_IDX,0,COMP_NE,0)
+PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("fpu","CPU has a floating point
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("htm","CPU has hardware transaction memory
instructions",SYS_CALL,SYS_CALL_TM_VER,0,COMP_GT,0)
+PPC_AIX_FEATURE("mma","CPU supports the matrix-multiply assist
instructions",SYS_CALL,SYS_CALL_MMA_VER,0,COMP_GT,0)
+PPC_AIX_FEATURE("mmu","CPU has a memory management
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE
ISA",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("power4","CPU supports ISA 200 (eg,
POWER4)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("power5","CPU supports ISA 202 (eg,
POWER5)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("power5+","CPU supports ISA 203 (eg,
POWER5+)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("power6x","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("ppc32","CPU supports 32-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("ppc601","CPU supports the old POWER ISA (eg,
601)",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address
swizzling",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("smt","CPU support simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,COMP_EQ,0x3)
+PPC_AIX_FEATURE("spe","CPU has a signal processing extension
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("true_le","CPU supports true little-endian
mode",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
+PPC_AIX_FEATURE("ucache","CPU has unified I/D
cache",USE_SYS_CONF,AIX_SYSCON_CACHE_IDX,0x00000002,COMP_EQ,0x00000002)
+PPC_AIX_FEATURE("vsx","CPU supports the vector-scalar
extension",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,COMP_GT,1)
+#undef PPC_AIX_FEATURE
+
// PPC_SYSTEMCONFIG_TYPE defines the IR data structure of kernel variable
// `_system_configuration`, that is found in the AIX OS header file:
</usr/include/sys/systemcfg.h>.
#ifndef PPC_SYSTEMCONFIG_TYPE
#define PPC_SYSTEMCONFIG_TYPE \
-Int32Ty, Int32Ty, Int32Ty
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int64Ty, Int32Ty, Int32Ty, Int32Ty, \
+Int32Ty, Int64Ty, Int64Ty, Int64Ty, Int64Ty, Int32Ty, \
+Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int64Ty, \
+Int32Ty, Int8Ty, Int8Ty, Int8Ty, Int8Ty, Int32Ty, \
+Int32Ty, Int16Ty, Int16Ty, llvm::ArrayType::get(Int32Ty,3), Int32Ty
#endif
#endif // !PPC_TGT_PARSER_UNDEF_MACROS
>From 814011f9a5c3c638a606aa0e19e55203769237b7 Mon Sep 17 00:00:00 2001
From: zhijian <zhij...@ca.ibm.com>
Date: Tue, 5 Mar 2024 14:23:22 -0500
Subject: [PATCH 2/6] rebased the code and add 4 new features
---
clang/lib/CodeGen/CGBuiltin.cpp | 7 ++--
clang/test/CodeGen/aix-builtin-cpu-supports.c | 36 +++++++++++++++++++
clang/test/Sema/aix-builtin-cpu-unsupports.c | 30 +++++-----------
.../llvm/TargetParser/PPCTargetParser.def | 4 +++
4 files changed, 53 insertions(+), 24 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1565e4103d9ef8..52c7744331605c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16654,7 +16654,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
\
.Case(NAME, {SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE})
#include "llvm/TargetParser/PPCTargetParser.def"
- );
+ .Default({AIX_BUILTIN_PPC_FALSE, 0, 0, 0}));
return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, 0, CompareOp,
CpuIdValue);
}
@@ -16681,12 +16681,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
typedef std::tuple<unsigned, unsigned, unsigned, unsigned, unsigned>
CPUSupportType;
std::tie(SupportMethod, FieldIdx, Mask, CompOp, Value) =
- static_cast<CPUSupportType>(StringSwitch<CPUSupportType>(CPUStr)
+ static_cast<CPUSupportType>(
+ StringSwitch<CPUSupportType>(CPUStr)
#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP,
\
VALUE)
\
.Case(NAME, {SUPPORT_METHOD, INDEX, MASK, COMP_OP, VALUE})
#include "llvm/TargetParser/PPCTargetParser.def"
- );
+ .Default({AIX_BUILTIN_PPC_FALSE, 0, 0, 0, 0}));
return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, Mask, CompOp,
Value);
}
diff --git a/clang/test/CodeGen/aix-builtin-cpu-supports.c
b/clang/test/CodeGen/aix-builtin-cpu-supports.c
index db144fd318f7b2..84aec5934586bc 100644
--- a/clang/test/CodeGen/aix-builtin-cpu-supports.c
+++ b/clang/test/CodeGen/aix-builtin-cpu-supports.c
@@ -5,6 +5,9 @@
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=46 -DOP=ugt -DBIT=i32 -DVALUE=0 \
// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+// RUN: echo "int main() { return __builtin_cpu_supports(\"archpmu\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"booke\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
@@ -15,6 +18,14 @@
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=262144 \
// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+// RUN: echo "int main() { return __builtin_cpu_supports(\"dscr\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=65536 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ebb\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=65536 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"efpdouble\");}" >
%t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
@@ -31,6 +42,18 @@
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=ugt -DLABLE=59 -DBIT=i64 -DVALUE=0 \
// RUN: --check-prefixes=CHECKOP,OPRT,SYSCALL
+// RUN: echo "int main() { return __builtin_cpu_supports(\"htm-nosc\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return
__builtin_cpu_supports(\"htm-no-suspend\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"ic_snoop\");}" >
%t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"isel\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"mma\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=ugt -DLABLE=62 -DBIT=i64 -DVALUE=0 \
// RUN: --check-prefixes=CHECKOP,OPRT,SYSCALL
@@ -38,6 +61,9 @@
// RUN: echo "int main() { return __builtin_cpu_supports(\"mmu\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
+// RUN: echo "int main() { return __builtin_cpu_supports(\"notb\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"arch_2_05\");}" >
%t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
@@ -92,6 +118,13 @@
// RUN: echo "int main() { return __builtin_cpu_supports(\"spe\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+// RUN: echo "int main() { return __builtin_cpu_supports(\"scv\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
+// RUN: echo "int main() { return __builtin_cpu_supports(\"tar\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=1 -DOP=uge -DBIT=i32 -DVALUE=65536 \
+// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"true_le\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=1 %s
@@ -99,6 +132,9 @@
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=5 -DMASK=2 -DOP=eq -DBIT=i32 -DVALUE=2 \
// RUN: --check-prefixes=CHECKOP,OPMASK,SYSCONF
+// RUN: echo "int main() { return __builtin_cpu_supports(\"vcrypto\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck -DBOOL=0 %s
+
// RUN: echo "int main() { return __builtin_cpu_supports(\"vsx\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DPOS=46 -DOP=ugt -DBIT=i32 -DVALUE=1 \
// RUN: --check-prefixes=CHECKOP,OPRT,SYSCONF
diff --git a/clang/test/Sema/aix-builtin-cpu-unsupports.c
b/clang/test/Sema/aix-builtin-cpu-unsupports.c
index 39cf3aea747f6e..e7ac780e4d0e5d 100644
--- a/clang/test/Sema/aix-builtin-cpu-unsupports.c
+++ b/clang/test/Sema/aix-builtin-cpu-unsupports.c
@@ -1,42 +1,30 @@
// RUN: %clang_cc1 -fsyntax-only -triple powerpc-ibm-aix7.2.0.0 -verify %s
int main(void) {
- if (__builtin_cpu_supports("aes")) // expected-error {{invalid cpu feature
string for builtin}}
+ if (__builtin_cpu_supports("aes")) // expected-warning {{invalid cpu feature
string for builtin}}
return 1;
- if (__builtin_cpu_supports("archpmu")) // expected-error {{invalid cpu
feature string for builtin}}
+ if (__builtin_cpu_supports("archpmu")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("dscr")) // expected-error {{invalid cpu feature
string for builtin}}
+ if (__builtin_cpu_supports("htm-nosc")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("ebb")) // expected-error {{invalid cpu feature
string for builtin}}
+ if (__builtin_cpu_supports("htm-no-suspend")) // expected-warning {{invalid
cpu feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("htm-nosc")) // expected-error {{invalid cpu
feature string for builtin}}
+ if (__builtin_cpu_supports("ic_snoop")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("htm-no-suspend")) // expected-error {{invalid
cpu feature string for builtin}}
+ if (__builtin_cpu_supports("ieee128")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("ic_snoop")) // expected-error {{invalid cpu
feature string for builtin}}
+ if (__builtin_cpu_supports("notb")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
- if (__builtin_cpu_supports("ieee128")) // expected-error {{invalid cpu
feature string for builtin}}
+ if (__builtin_cpu_supports("scv")) // expected-warning {{invalid cpu feature
string for builtin}}
return 1;
- if (__builtin_cpu_supports("isel")) // expected-error {{invalid cpu feature
string for builtin}}
- return 1;
-
- if (__builtin_cpu_supports("notb")) // expected-error {{invalid cpu feature
string for builtin}}
- return 1;
-
- if (__builtin_cpu_supports("scv")) // expected-error {{invalid cpu feature
string for builtin}}
- return 1;
-
- if (__builtin_cpu_supports("tar")) // expected-error {{invalid cpu feature
string for builtin}}
- return 1;
-
- if (__builtin_cpu_supports("vcrypto")) // expected-error {{invalid cpu
feature string for builtin}}
+ if (__builtin_cpu_supports("vcrypto")) // expected-warning {{invalid cpu
feature string for builtin}}
return 1;
}
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index bae4baf8422609..583bdf37e291ad 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -206,10 +206,13 @@ PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA
category",AIX_BUILTIN_PPC
PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband
engine",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number)
instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC10_VALUE)
PPC_AIX_FEATURE("dfp","CPU has a decimal floating point
unit",USE_SYS_CONF,AIX_SYSCON_DFP_IDX,0,COMP_NE,0)
+PPC_AIX_FEATURE("dscr","CPU supports the data stream control
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("ebb","CPU supports event base
branching",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
PPC_AIX_FEATURE("fpu","CPU has a floating point
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
PPC_AIX_FEATURE("htm","CPU has hardware transaction memory
instructions",SYS_CALL,SYS_CALL_TM_VER,0,COMP_GT,0)
+PPC_AIX_FEATURE("isel","CPU supports the integer select
instruction",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
PPC_AIX_FEATURE("mma","CPU supports the matrix-multiply assist
instructions",SYS_CALL,SYS_CALL_MMA_VER,0,COMP_GT,0)
PPC_AIX_FEATURE("mmu","CPU has a memory management
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
PPC_AIX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE
ISA",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
@@ -223,6 +226,7 @@ PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode
execution",AIX_BUILTIN_PPC_TRU
PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address
swizzling",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
PPC_AIX_FEATURE("smt","CPU support simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,COMP_EQ,0x3)
PPC_AIX_FEATURE("spe","CPU has a signal processing extension
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
+PPC_AIX_FEATURE("tar","CPU supports the target address
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
PPC_AIX_FEATURE("true_le","CPU supports true little-endian
mode",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
PPC_AIX_FEATURE("ucache","CPU has unified I/D
cache",USE_SYS_CONF,AIX_SYSCON_CACHE_IDX,0x00000002,COMP_EQ,0x00000002)
PPC_AIX_FEATURE("vsx","CPU supports the vector-scalar
extension",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,COMP_GT,1)
>From 3867877e8fbddf40b48f1343a37a6e1bfe8c1005 Mon Sep 17 00:00:00 2001
From: zhijian <zhij...@ca.ibm.com>
Date: Wed, 6 Mar 2024 16:29:05 -0500
Subject: [PATCH 3/6] address comment
---
clang/lib/CodeGen/CGBuiltin.cpp | 44 +++----
.../CodeGen/multi-aix-builtin-cpu-supports.c | 43 +++++++
.../llvm/TargetParser/PPCTargetParser.def | 109 ++++++++----------
3 files changed, 109 insertions(+), 87 deletions(-)
create mode 100644 clang/test/CodeGen/multi-aix-builtin-cpu-supports.c
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 52c7744331605c..010f5485f7d1c2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16570,7 +16570,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned Mask, unsigned CompOp,
+ unsigned Mask, CmpInst::Predicate CompOp,
unsigned OpValue) -> Value * {
if (SupportMethod == AIX_BUILTIN_PPC_FALSE)
return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
@@ -16608,25 +16608,6 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
if (Mask)
FieldValue = Builder.CreateAnd(FieldValue, Mask);
- CmpInst::Predicate PreOp;
- switch (CompOp) {
- case COMP_EQ:
- PreOp = ICmpInst::ICMP_EQ;
- break;
- case COMP_GT:
- PreOp = ICmpInst::ICMP_UGT;
- break;
- case COMP_GE:
- PreOp = ICmpInst::ICMP_UGE;
- break;
- case COMP_NE:
- PreOp = ICmpInst::ICMP_NE;
- break;
- default:
- llvm_unreachable(
- "Compare type does not match types defined in PPCTargetParser.def!");
- }
-
llvm::Type *ValueType = FieldValue->getType();
bool IsValueType64Bit = ValueType->isIntegerTy(64);
assert(
@@ -16634,7 +16615,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
"Only 32/64-bit integers are supported in GenAIXPPCBuiltinCpuExpr().");
return Builder.CreateICmp(
- PreOp, FieldValue,
+ CompOp, FieldValue,
ConstantInt::get(IsValueType64Bit ? Int64Ty : Int32Ty, OpValue));
};
@@ -16647,14 +16628,17 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
llvm::Triple Triple = getTarget().getTriple();
if (Triple.isOSAIX()) {
- unsigned SupportMethod, FieldIdx, CompareOp, CpuIdValue;
- typedef std::tuple<unsigned, unsigned, unsigned, unsigned> CPUType;
+ unsigned SupportMethod, FieldIdx, CpuIdValue;
+ CmpInst::Predicate CompareOp;
+ typedef std::tuple<unsigned, unsigned, CmpInst::Predicate, unsigned>
+ CPUType;
std::tie(SupportMethod, FieldIdx, CompareOp, CpuIdValue) =
static_cast<CPUType>(StringSwitch<CPUType>(CPUStr)
#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
\
.Case(NAME, {SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE})
#include "llvm/TargetParser/PPCTargetParser.def"
- .Default({AIX_BUILTIN_PPC_FALSE, 0, 0, 0}));
+ .Default({AIX_BUILTIN_PPC_FALSE, 0,
+ CmpInst::Predicate(), 0}));
return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, 0, CompareOp,
CpuIdValue);
}
@@ -16677,17 +16661,19 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
if (Triple.isOSAIX()) {
- unsigned SupportMethod, FieldIdx, Mask, CompOp, Value;
- typedef std::tuple<unsigned, unsigned, unsigned, unsigned, unsigned>
+ unsigned SupportMethod, FieldIdx, Mask, Value;
+ CmpInst::Predicate CompOp;
+ typedef std::tuple<unsigned, unsigned, unsigned, CmpInst::Predicate,
+ unsigned>
CPUSupportType;
std::tie(SupportMethod, FieldIdx, Mask, CompOp, Value) =
- static_cast<CPUSupportType>(
- StringSwitch<CPUSupportType>(CPUStr)
+ static_cast<CPUSupportType>(StringSwitch<CPUSupportType>(CPUStr)
#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP,
\
VALUE)
\
.Case(NAME, {SUPPORT_METHOD, INDEX, MASK, COMP_OP, VALUE})
#include "llvm/TargetParser/PPCTargetParser.def"
- .Default({AIX_BUILTIN_PPC_FALSE, 0, 0, 0, 0}));
+ .Default({AIX_BUILTIN_PPC_FALSE, 0,
0,
+ CmpInst::Predicate(), 0}));
return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, Mask, CompOp,
Value);
}
diff --git a/clang/test/CodeGen/multi-aix-builtin-cpu-supports.c
b/clang/test/CodeGen/multi-aix-builtin-cpu-supports.c
new file mode 100644
index 00000000000000..36b5da33959b87
--- /dev/null
+++ b/clang/test/CodeGen/multi-aix-builtin-cpu-supports.c
@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %s |
FileCheck %s
+
+int main() {
+ int ret = 0;
+ ret += __builtin_cpu_supports("vsx");
+ ret += __builtin_cpu_supports("htm");
+ ret += __builtin_cpu_supports("cellbe");
+ ret += __builtin_cpu_supports("power4");
+ return ret;
+}
+
+// CHECK: @_system_configuration = external global { i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32,
i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8, i8,
i8, i32, i32, i16, i16, [3 x i32], i32 }
+// CHECK-EMPTY:
+// CHECK-NEXT: ; Function Attrs: noinline nounwind optnone
+// CHECK-NEXT: define i32 @main() #0 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: %retval = alloca i32, align 4
+// CHECK-NEXT: %ret = alloca i32, align 4
+// CHECK-NEXT: store i32 0, ptr %retval, align 4
+// CHECK-NEXT: store i32 0, ptr %ret, align 4
+// CHECK-NEXT: %0 = load i32, ptr getelementptr inbounds ({ i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32,
i32, i32, i64, i64, i64, i64, i32, i32, i32, i32, i32, i32, i64, i32, i8, i8,
i8, i8, i32, i32, i16, i16, [3 x i32], i32 }, ptr @_system_configuration, i32
0, i32 46), align 4
+// CHECK-NEXT: %1 = icmp ugt i32 %0, 1
+// CHECK-NEXT: %conv = zext i1 %1 to i32
+// CHECK-NEXT: %2 = load i32, ptr %ret, align 4
+// CHECK-NEXT: %add = add nsw i32 %2, %conv
+// CHECK-NEXT: store i32 %add, ptr %ret, align 4
+// CHECK-NEXT: %3 = call i64 @getsystemcfg(i32 59)
+// CHECK-NEXT: %4 = icmp ugt i64 %3, 0
+// CHECK-NEXT: %conv1 = zext i1 %4 to i32
+// CHECK-NEXT: %5 = load i32, ptr %ret, align 4
+// CHECK-NEXT: %add2 = add nsw i32 %5, %conv1
+// CHECK-NEXT: store i32 %add2, ptr %ret, align 4
+// CHECK-NEXT: %6 = load i32, ptr %ret, align 4
+// CHECK-NEXT: %add3 = add nsw i32 %6, 0
+// CHECK-NEXT: store i32 %add3, ptr %ret, align 4
+// CHECK-NEXT: %7 = load i32, ptr %ret, align 4
+// CHECK-NEXT: %add4 = add nsw i32 %7, 1
+// CHECK-NEXT: store i32 %add4, ptr %ret, align 4
+// CHECK-NEXT: %8 = load i32, ptr %ret, align 4
+// CHECK-NEXT: ret i32 %8
+// CHECK-NEXT: }
+// CHECK-EMPTY:
+// CHECK-NEXT: declare i64 @getsystemcfg(i32)
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index 583bdf37e291ad..8557568d9a62e1 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -150,13 +150,6 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
#define SYS_CALL 3
-
- // Supported COMPARE_OP values.
- #define COMP_EQ 0
- #define COMP_GT 1
- #define COMP_GE 2
- #define COMP_NE 3
-
#endif
// The value of SUPPORT_METHOD can be AIX_BUILTIN_PPC_TRUE,
@@ -173,63 +166,63 @@ PPC_LNX_CPU("power10",47)
#endif
// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on
Power7 and up.
-PPC_AIX_CPU("power4",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc970",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power5",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power5+",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power6",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc-cell-be",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power6x",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppca2",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc405",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc440",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc464",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc476",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power7",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC7_VALUE)
-PPC_AIX_CPU("power8",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC8_VALUE)
-PPC_AIX_CPU("power9",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC9_VALUE)
-PPC_AIX_CPU("power10",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC10_VALUE)
+PPC_AIX_CPU("power4",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc970",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power5",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power5+",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power6",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc-cell-be",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power6x",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppca2",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc405",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc440",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc464",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc476",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power7",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC7_VALUE)
+PPC_AIX_CPU("power8",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC8_VALUE)
+PPC_AIX_CPU("power9",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC9_VALUE)
+PPC_AIX_CPU("power10",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC10_VALUE)
#undef PPC_AIX_CPU
#ifndef PPC_AIX_FEATURE
#define PPC_AIX_FEATURE(NAME,DESC,SUPPORT_METHOD,INDEX,MASK,COMPARE_OP,VALUE)
#endif
-PPC_AIX_FEATURE("4xxmac","4xx CPU has a Multiply
Accumulator",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector
Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,COMP_GT,0)
-PPC_AIX_FEATURE("arch_2_05","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("arch_2_06","CPU supports ISA 206 (eg,
POWER7)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC7_VALUE)
-PPC_AIX_FEATURE("arch_2_07","CPU supports ISA 207 (eg,
POWER8)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
-PPC_AIX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC9_VALUE)
-PPC_AIX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC10_VALUE)
-PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA
category",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband
engine",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number)
instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC10_VALUE)
-PPC_AIX_FEATURE("dfp","CPU has a decimal floating point
unit",USE_SYS_CONF,AIX_SYSCON_DFP_IDX,0,COMP_NE,0)
-PPC_AIX_FEATURE("dscr","CPU supports the data stream control
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
-PPC_AIX_FEATURE("ebb","CPU supports event base
branching",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
-PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("fpu","CPU has a floating point
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("htm","CPU has hardware transaction memory
instructions",SYS_CALL,SYS_CALL_TM_VER,0,COMP_GT,0)
-PPC_AIX_FEATURE("isel","CPU supports the integer select
instruction",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("mma","CPU supports the matrix-multiply assist
instructions",SYS_CALL,SYS_CALL_MMA_VER,0,COMP_GT,0)
-PPC_AIX_FEATURE("mmu","CPU has a memory management
unit",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE
ISA",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("power4","CPU supports ISA 200 (eg,
POWER4)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("power5","CPU supports ISA 202 (eg,
POWER5)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("power5+","CPU supports ISA 203 (eg,
POWER5+)",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("power6x","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("ppc32","CPU supports 32-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("ppc601","CPU supports the old POWER ISA (eg,
601)",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address
swizzling",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("smt","CPU support simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,COMP_EQ,0x3)
-PPC_AIX_FEATURE("spe","CPU has a signal processing extension
unit",AIX_BUILTIN_PPC_FALSE,0,0,0,0)
-PPC_AIX_FEATURE("tar","CPU supports the target address
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,COMP_GE,AIX_PPC8_VALUE)
-PPC_AIX_FEATURE("true_le","CPU supports true little-endian
mode",AIX_BUILTIN_PPC_TRUE,0,0,0,0)
-PPC_AIX_FEATURE("ucache","CPU has unified I/D
cache",USE_SYS_CONF,AIX_SYSCON_CACHE_IDX,0x00000002,COMP_EQ,0x00000002)
-PPC_AIX_FEATURE("vsx","CPU supports the vector-scalar
extension",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,COMP_GT,1)
+PPC_AIX_FEATURE("4xxmac","4xx CPU has a Multiply
Accumulator",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector
Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::ICMP_UGT,0)
+PPC_AIX_FEATURE("arch_2_05","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("arch_2_06","CPU supports ISA 206 (eg,
POWER7)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC7_VALUE)
+PPC_AIX_FEATURE("arch_2_07","CPU supports ISA 207 (eg,
POWER8)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC9_VALUE)
+PPC_AIX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA
category",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband
engine",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number)
instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("dfp","CPU has a decimal floating point
unit",USE_SYS_CONF,AIX_SYSCON_DFP_IDX,0,ICmpInst::ICMP_NE,0)
+PPC_AIX_FEATURE("dscr","CPU supports the data stream control
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("ebb","CPU supports event base
branching",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point
unit",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("fpu","CPU has a floating point
unit",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("htm","CPU has hardware transaction memory
instructions",SYS_CALL,SYS_CALL_TM_VER,0,ICmpInst::ICMP_UGT,0)
+PPC_AIX_FEATURE("isel","CPU supports the integer select
instruction",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("mma","CPU supports the matrix-multiply assist
instructions",SYS_CALL,SYS_CALL_MMA_VER,0,ICmpInst::ICMP_UGT,0)
+PPC_AIX_FEATURE("mmu","CPU has a memory management
unit",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE
ISA",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("power4","CPU supports ISA 200 (eg,
POWER4)",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("power5","CPU supports ISA 202 (eg,
POWER5)",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("power5+","CPU supports ISA 203 (eg,
POWER5+)",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("power6x","CPU supports ISA 205 (eg,
POWER6)",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("ppc32","CPU supports 32-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("ppc601","CPU supports the old POWER ISA (eg,
601)",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address
swizzling",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("smt","CPU support simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,ICmpInst::ICMP_EQ,0x3)
+PPC_AIX_FEATURE("spe","CPU has a signal processing extension
unit",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("tar","CPU supports the target address
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("true_le","CPU supports true little-endian
mode",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("ucache","CPU has unified I/D
cache",USE_SYS_CONF,AIX_SYSCON_CACHE_IDX,0x00000002,ICmpInst::ICMP_EQ,0x00000002)
+PPC_AIX_FEATURE("vsx","CPU supports the vector-scalar
extension",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::ICMP_UGT,1)
#undef PPC_AIX_FEATURE
// PPC_SYSTEMCONFIG_TYPE defines the IR data structure of kernel variable
>From 17ce0bee65d3f14e1471dfc2a7f2cd005adbdd48 Mon Sep 17 00:00:00 2001
From: zhijian <zhij...@ca.ibm.com>
Date: Wed, 6 Mar 2024 16:56:31 -0500
Subject: [PATCH 4/6] address comment
---
llvm/include/llvm/TargetParser/PPCTargetParser.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index 8557568d9a62e1..f3c77aa760f1c6 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -160,6 +160,8 @@ PPC_LNX_CPU("power10",47)
// When the SUPPORT_METHOD value is set to SYS_CALL, the return value depends
// on comparing a VALUE with the return value of calling `getsystemcfg`
// with the parameter INDEX, which is then masked by Mask.
+// AIX_BUILTIN_PPC_TRUE and AIX_BUILTIN_PPC_FALSE are for features
+// that are supported or unsupported on all systems respectively.
#ifndef PPC_AIX_CPU
#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
>From 29b5ecbb5a2ac88ddc4f421494aecfe53ce65eb6 Mon Sep 17 00:00:00 2001
From: zhijian lin <zhij...@ca.ibm.com>
Date: Mon, 18 Mar 2024 13:46:43 -0400
Subject: [PATCH 5/6] Update llvm/include/llvm/TargetParser/PPCTargetParser.def
Co-authored-by: Amy Kwan <amy.kw...@ibm.com>
---
llvm/include/llvm/TargetParser/PPCTargetParser.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index f3c77aa760f1c6..e5c6015d6ee30f 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -219,7 +219,7 @@ PPC_AIX_FEATURE("ppc32","CPU supports 32-bit mode
execution",AIX_BUILTIN_PPC_TRU
PPC_AIX_FEATURE("ppc601","CPU supports the old POWER ISA (eg,
601)",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode
execution",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address
swizzling",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
-PPC_AIX_FEATURE("smt","CPU support simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,ICmpInst::ICMP_EQ,0x3)
+PPC_AIX_FEATURE("smt","CPU supports simultaneous
multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,ICmpInst::ICMP_EQ,0x3)
PPC_AIX_FEATURE("spe","CPU has a signal processing extension
unit",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
PPC_AIX_FEATURE("tar","CPU supports the target address
register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
PPC_AIX_FEATURE("true_le","CPU supports true little-endian
mode",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
>From 079c30d147dd01b62f7a55e647aa0c119b351295 Mon Sep 17 00:00:00 2001
From: zhijian <zhij...@ca.ibm.com>
Date: Tue, 19 Mar 2024 16:23:09 -0400
Subject: [PATCH 6/6] address comment
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 010f5485f7d1c2..3882c0abf8a8c9 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16602,7 +16602,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
FieldValue =
Builder.CreateCall(Func, {ConstantInt::get(Int32Ty, FieldIdx)});
}
- assert((FieldValue != nullptr) &&
+ assert(FieldValue &&
"SupportMethod value is not defined in PPCTargetParser.def.");
if (Mask)
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