Author: Kuba (Brecka) Mracek Date: 2024-03-13T20:04:30-07:00 New Revision: b84ce9979990283aa4398ad5a654b8b283baa532
URL: https://github.com/llvm/llvm-project/commit/b84ce9979990283aa4398ad5a654b8b283baa532 DIFF: https://github.com/llvm/llvm-project/commit/b84ce9979990283aa4398ad5a654b8b283baa532.diff LOG: [clang] Define SwiftInfo for RISCVTargetCodeGenInfo (#82152) For Embedded Swift, let's unblock building for RISC-V boards (e.g. ESP32-C6). This isn't trying to add full RISC-V support to Swift / Embedded Swift, it's just fixing the immediate blocker (not having SwiftInfo defined blocks all compilations). Added: Modified: clang/lib/CodeGen/Targets/RISCV.cpp clang/test/CodeGenCXX/arm-swiftcall.cpp Removed: ################################################################################ diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp index dec6540230a60f..9a79424c4612ce 100644 --- a/clang/lib/CodeGen/Targets/RISCV.cpp +++ b/clang/lib/CodeGen/Targets/RISCV.cpp @@ -529,7 +529,10 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo { RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen, bool EABI) : TargetCodeGenInfo( - std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {} + std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) { + SwiftInfo = + std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false); + } void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const override { diff --git a/clang/test/CodeGenCXX/arm-swiftcall.cpp b/clang/test/CodeGenCXX/arm-swiftcall.cpp index e60c1482700a4b..45eea7bfd853b9 100644 --- a/clang/test/CodeGenCXX/arm-swiftcall.cpp +++ b/clang/test/CodeGenCXX/arm-swiftcall.cpp @@ -1,5 +1,9 @@ // RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03 | FileCheck %s -check-prefixes=CHECK +// For now just check that the RISC-V triples are accepted, but don't check the IR, as swiftcall is not yet supported. +// RUN: %clang_cc1 -triple riscv32-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03 +// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03 + // This isn't really testing anything ARM-specific; it's just a convenient // 32-bit platform. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
