Author: ctopper
Date: Sun Nov 13 01:26:34 2016
New Revision: 286757
URL: http://llvm.org/viewvc/llvm-project?rev=286757&view=rev
Log:
[AVX-512] Replace masked dword and qword variable shift builtins with unmasked
builtins and a select.
This is part of a set of changes to allow InstCombine in the backend to
optimize variable shifts without having to know about masking.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/lib/Headers/avx512vlintrin.h
cfe/trunk/test/CodeGen/avx512f-builtins.c
cfe/trunk/test/CodeGen/avx512vl-builtins.c
Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=286757&r1=286756&r2=286757&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Sun Nov 13 01:26:34 2016
@@ -1373,8 +1373,8 @@ TARGET_BUILTIN(__builtin_ia32_psrlqi512,
TARGET_BUILTIN(__builtin_ia32_psrav32hi_mask,
"V32sV32sV32sV32sUi","","avx512bw")
TARGET_BUILTIN(__builtin_ia32_psrav16hi_mask,
"V16sV16sV16sV16sUs","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_psrav8hi_mask,
"V8sV8sV8sV8sUc","","avx512bw,avx512vl")
-TARGET_BUILTIN(__builtin_ia32_psravq128_mask,
"V2LLiV2LLiV2LLiV2LLiUc","","avx512vl")
-TARGET_BUILTIN(__builtin_ia32_psravq256_mask,
"V4LLiV4LLiV4LLiV4LLiUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_psravq128, "V2LLiV2LLiV2LLi","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_psravq256, "V4LLiV4LLiV4LLi","","avx512vl")
TARGET_BUILTIN(__builtin_ia32_psraw512, "V32sV32sV8s","","avx512bw")
TARGET_BUILTIN(__builtin_ia32_psrawi512, "V32sV32si","","avx512bw")
TARGET_BUILTIN(__builtin_ia32_psrlw512, "V32sV32sV8s","","avx512bw")
@@ -1547,16 +1547,16 @@ TARGET_BUILTIN(__builtin_ia32_psraqi128,
TARGET_BUILTIN(__builtin_ia32_psraqi256, "V4LLiV4LLii","","avx512vl")
TARGET_BUILTIN(__builtin_ia32_pslld512, "V16iV16iV4i","","avx512f")
TARGET_BUILTIN(__builtin_ia32_psllq512, "V8LLiV8LLiV2LLi","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psllv16si_mask,
"V16iV16iV16iV16iUs","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psllv8di_mask,
"V8LLiV8LLiV8LLiV8LLiUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psllv16si, "V16iV16iV16i","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psllv8di, "V8LLiV8LLiV8LLi","","avx512f")
TARGET_BUILTIN(__builtin_ia32_psrad512, "V16iV16iV4i","","avx512f")
TARGET_BUILTIN(__builtin_ia32_psraq512, "V8LLiV8LLiV2LLi","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psrav16si_mask,
"V16iV16iV16iV16iUs","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psrav8di_mask,
"V8LLiV8LLiV8LLiV8LLiUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psrav16si, "V16iV16iV16i","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psrav8di, "V8LLiV8LLiV8LLi","","avx512f")
TARGET_BUILTIN(__builtin_ia32_psrld512, "V16iV16iV4i","","avx512f")
TARGET_BUILTIN(__builtin_ia32_psrlq512, "V8LLiV8LLiV2LLi","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psrlv16si_mask,
"V16iV16iV16iV16iUs","","avx512f")
-TARGET_BUILTIN(__builtin_ia32_psrlv8di_mask,
"V8LLiV8LLiV8LLiV8LLiUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psrlv16si, "V16iV16iV16i","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_psrlv8di, "V8LLiV8LLiV8LLi","","avx512f")
TARGET_BUILTIN(__builtin_ia32_pternlogd512_mask,
"V16iV16iV16iV16iIiUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_pternlogd512_maskz,
"V16iV16iV16iV16iIiUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_pternlogq512_mask,
"V8LLiV8LLiV8LLiV8LLiIiUc","","avx512f")
Modified: cfe/trunk/lib/Headers/avx512fintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=286757&r1=286756&r2=286757&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/avx512fintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512fintrin.h Sun Nov 13 01:26:34 2016
@@ -6060,61 +6060,47 @@ _mm512_maskz_sll_epi64(__mmask8 __U, __m
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_sllv_epi32 (__m512i __X, __m512i __Y)
+_mm512_sllv_epi32(__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) -1);
+ return (__m512i)__builtin_ia32_psllv16si((__v16si)__X, (__v16si)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_sllv_epi32 (__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_mask_sllv_epi32(__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si) __W,
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_sllv_epi32(__X,
__Y),
+ (__v16si)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_sllv_epi32 (__mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_sllv_epi32(__mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_sllv_epi32(__X,
__Y),
+ (__v16si)_mm512_setzero_si512());
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_sllv_epi64 (__m512i __X, __m512i __Y)
+_mm512_sllv_epi64(__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_undefined_pd (),
- (__mmask8) -1);
+ return (__m512i)__builtin_ia32_psllv8di((__v8di)__X, (__v8di)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_sllv_epi64 (__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_mask_sllv_epi64(__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di) __W,
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_sllv_epi64(__X,
__Y),
+ (__v8di)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_sllv_epi64 (__mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_sllv_epi64(__mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psllv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_setzero_si512 (),
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_sllv_epi64(__X,
__Y),
+ (__v8di)_mm512_setzero_si512());
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
@@ -6162,61 +6148,47 @@ _mm512_maskz_sra_epi64(__mmask8 __U, __m
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_srav_epi32 (__m512i __X, __m512i __Y)
+_mm512_srav_epi32(__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) -1);
+ return (__m512i)__builtin_ia32_psrav16si((__v16si)__X, (__v16si)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_srav_epi32 (__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_mask_srav_epi32(__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si) __W,
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_srav_epi32(__X,
__Y),
+ (__v16si)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_srav_epi32 (__mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_srav_epi32(__mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_srav_epi32(__X,
__Y),
+ (__v16si)_mm512_setzero_si512());
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_srav_epi64 (__m512i __X, __m512i __Y)
+_mm512_srav_epi64(__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_setzero_si512 (),
- (__mmask8) -1);
+ return (__m512i)__builtin_ia32_psrav8di((__v8di)__X, (__v8di)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_srav_epi64 (__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_mask_srav_epi64(__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di) __W,
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_srav_epi64(__X,
__Y),
+ (__v8di)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_srav_epi64 (__mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_srav_epi64(__mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrav8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_setzero_si512 (),
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_srav_epi64(__X,
__Y),
+ (__v8di)_mm512_setzero_si512());
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
@@ -6264,61 +6236,47 @@ _mm512_maskz_srl_epi64(__mmask8 __U, __m
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_srlv_epi32 (__m512i __X, __m512i __Y)
+_mm512_srlv_epi32(__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) -1);
+ return (__m512i)__builtin_ia32_psrlv16si((__v16si)__X, (__v16si)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_srlv_epi32 (__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_mask_srlv_epi32(__m512i __W, __mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si) __W,
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_srlv_epi32(__X,
__Y),
+ (__v16si)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_srlv_epi32 (__mmask16 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_srlv_epi32(__mmask16 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv16si_mask ((__v16si) __X,
- (__v16si) __Y,
- (__v16si)
- _mm512_setzero_si512 (),
- (__mmask16) __U);
+ return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
+ (__v16si)_mm512_srlv_epi32(__X,
__Y),
+ (__v16si)_mm512_setzero_si512());
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_srlv_epi64 (__m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_setzero_si512 (),
- (__mmask8) -1);
+ return (__m512i)__builtin_ia32_psrlv8di((__v8di)__X, (__v8di)__Y);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_mask_srlv_epi64 (__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_mask_srlv_epi64(__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di) __W,
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_srlv_epi64(__X,
__Y),
+ (__v8di)__W);
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
-_mm512_maskz_srlv_epi64 (__mmask8 __U, __m512i __X, __m512i __Y)
+_mm512_maskz_srlv_epi64(__mmask8 __U, __m512i __X, __m512i __Y)
{
- return (__m512i) __builtin_ia32_psrlv8di_mask ((__v8di) __X,
- (__v8di) __Y,
- (__v8di)
- _mm512_setzero_si512 (),
- (__mmask8) __U);
+ return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
+ (__v8di)_mm512_srlv_epi64(__X,
__Y),
+ (__v8di)_mm512_setzero_si512());
}
#define _mm512_ternarylogic_epi32(A, B, C, imm) __extension__ ({ \
Modified: cfe/trunk/lib/Headers/avx512vlintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512vlintrin.h?rev=286757&r1=286756&r2=286757&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/avx512vlintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512vlintrin.h Sun Nov 13 01:26:34 2016
@@ -5484,63 +5484,47 @@ _mm256_maskz_srav_epi32(__mmask8 __U, __
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_srav_epi64 (__m128i __X, __m128i __Y)
+_mm_srav_epi64(__m128i __X, __m128i __Y)
{
- return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
- (__v2di) __Y,
- (__v2di)
- _mm_setzero_di (),
- (__mmask8) -1);
+ return (__m128i)__builtin_ia32_psravq128((__v2di)__X, (__v2di)__Y);
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_mask_srav_epi64 (__m128i __W, __mmask8 __U, __m128i __X,
- __m128i __Y)
+_mm_mask_srav_epi64(__m128i __W, __mmask8 __U, __m128i __X, __m128i __Y)
{
- return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
- (__v2di) __Y,
- (__v2di) __W,
- (__mmask8) __U);
+ return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
+ (__v2di)_mm_srav_epi64(__X, __Y),
+ (__v2di)__W);
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_maskz_srav_epi64 (__mmask8 __U, __m128i __X, __m128i __Y)
+_mm_maskz_srav_epi64(__mmask8 __U, __m128i __X, __m128i __Y)
{
- return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
- (__v2di) __Y,
- (__v2di)
- _mm_setzero_di (),
- (__mmask8) __U);
+ return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
+ (__v2di)_mm_srav_epi64(__X, __Y),
+ (__v2di)_mm_setzero_di());
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
-_mm256_srav_epi64 (__m256i __X, __m256i __Y)
+_mm256_srav_epi64(__m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
- (__v4di) __Y,
- (__v4di)
- _mm256_setzero_si256 (),
- (__mmask8) -1);
+ return (__m256i)__builtin_ia32_psravq256((__v4di)__X, (__v4di) __Y);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
-_mm256_mask_srav_epi64 (__m256i __W, __mmask8 __U, __m256i __X,
- __m256i __Y)
+_mm256_mask_srav_epi64(__m256i __W, __mmask8 __U, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
- (__v4di) __Y,
- (__v4di) __W,
- (__mmask8) __U);
+ return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
+ (__v4di)_mm256_srav_epi64(__X,
__Y),
+ (__v4di)__W);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_maskz_srav_epi64 (__mmask8 __U, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
- (__v4di) __Y,
- (__v4di)
- _mm256_setzero_si256 (),
- (__mmask8) __U);
+ return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
+ (__v4di)_mm256_srav_epi64(__X,
__Y),
+ (__v4di)_mm256_setzero_si256());
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
Modified: cfe/trunk/test/CodeGen/avx512f-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512f-builtins.c?rev=286757&r1=286756&r2=286757&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/avx512f-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx512f-builtins.c Sun Nov 13 01:26:34 2016
@@ -4225,37 +4225,41 @@ __m512i test_mm512_maskz_sll_epi64(__mma
__m512i test_mm512_sllv_epi32(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_sllv_epi32
- // CHECK: @llvm.x86.avx512.mask.psllv.d
+ // CHECK: @llvm.x86.avx512.psllv.d.512
return _mm512_sllv_epi32(__X, __Y);
}
__m512i test_mm512_mask_sllv_epi32(__m512i __W, __mmask16 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_sllv_epi32
- // CHECK: @llvm.x86.avx512.mask.psllv.d
+ // CHECK: @llvm.x86.avx512.psllv.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_mask_sllv_epi32(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_sllv_epi32(__mmask16 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_sllv_epi32
- // CHECK: @llvm.x86.avx512.mask.psllv.d
+ // CHECK: @llvm.x86.avx512.psllv.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_maskz_sllv_epi32(__U, __X, __Y);
}
__m512i test_mm512_sllv_epi64(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_sllv_epi64
- // CHECK: @llvm.x86.avx512.mask.psllv.q
+ // CHECK: @llvm.x86.avx512.psllv.q.512
return _mm512_sllv_epi64(__X, __Y);
}
__m512i test_mm512_mask_sllv_epi64(__m512i __W, __mmask8 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_sllv_epi64
- // CHECK: @llvm.x86.avx512.mask.psllv.q
+ // CHECK: @llvm.x86.avx512.psllv.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_mask_sllv_epi64(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_sllv_epi64(__mmask8 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_sllv_epi64
- // CHECK: @llvm.x86.avx512.mask.psllv.q
+ // CHECK: @llvm.x86.avx512.psllv.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_maskz_sllv_epi64(__U, __X, __Y);
}
@@ -4301,37 +4305,41 @@ __m512i test_mm512_maskz_sra_epi64(__mma
__m512i test_mm512_srav_epi32(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_srav_epi32
- // CHECK: @llvm.x86.avx512.mask.psrav.d
+ // CHECK: @llvm.x86.avx512.psrav.d.512
return _mm512_srav_epi32(__X, __Y);
}
__m512i test_mm512_mask_srav_epi32(__m512i __W, __mmask16 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_srav_epi32
- // CHECK: @llvm.x86.avx512.mask.psrav.d
+ // CHECK: @llvm.x86.avx512.psrav.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_mask_srav_epi32(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_srav_epi32(__mmask16 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_srav_epi32
- // CHECK: @llvm.x86.avx512.mask.psrav.d
+ // CHECK: @llvm.x86.avx512.psrav.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_maskz_srav_epi32(__U, __X, __Y);
}
__m512i test_mm512_srav_epi64(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q
+ // CHECK: @llvm.x86.avx512.psrav.q.512
return _mm512_srav_epi64(__X, __Y);
}
__m512i test_mm512_mask_srav_epi64(__m512i __W, __mmask8 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q
+ // CHECK: @llvm.x86.avx512.psrav.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_mask_srav_epi64(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_srav_epi64(__mmask8 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q
+ // CHECK: @llvm.x86.avx512.psrav.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_maskz_srav_epi64(__U, __X, __Y);
}
@@ -4377,37 +4385,41 @@ __m512i test_mm512_maskz_srl_epi64(__mma
__m512i test_mm512_srlv_epi32(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_srlv_epi32
- // CHECK: @llvm.x86.avx512.mask.psrlv.d
+ // CHECK: @llvm.x86.avx512.psrlv.d.512
return _mm512_srlv_epi32(__X, __Y);
}
__m512i test_mm512_mask_srlv_epi32(__m512i __W, __mmask16 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_srlv_epi32
- // CHECK: @llvm.x86.avx512.mask.psrlv.d
+ // CHECK: @llvm.x86.avx512.psrlv.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_mask_srlv_epi32(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_srlv_epi32(__mmask16 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_srlv_epi32
- // CHECK: @llvm.x86.avx512.mask.psrlv.d
+ // CHECK: @llvm.x86.avx512.psrlv.d.512
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_maskz_srlv_epi32(__U, __X, __Y);
}
__m512i test_mm512_srlv_epi64(__m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_srlv_epi64
- // CHECK: @llvm.x86.avx512.mask.psrlv.q
+ // CHECK: @llvm.x86.avx512.psrlv.q.512
return _mm512_srlv_epi64(__X, __Y);
}
__m512i test_mm512_mask_srlv_epi64(__m512i __W, __mmask8 __U, __m512i __X,
__m512i __Y) {
// CHECK-LABEL: @test_mm512_mask_srlv_epi64
- // CHECK: @llvm.x86.avx512.mask.psrlv.q
+ // CHECK: @llvm.x86.avx512.psrlv.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_mask_srlv_epi64(__W, __U, __X, __Y);
}
__m512i test_mm512_maskz_srlv_epi64(__mmask8 __U, __m512i __X, __m512i __Y) {
// CHECK-LABEL: @test_mm512_maskz_srlv_epi64
- // CHECK: @llvm.x86.avx512.mask.psrlv.q
+ // CHECK: @llvm.x86.avx512.psrlv.q.512
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
return _mm512_maskz_srlv_epi64(__U, __X, __Y);
}
Modified: cfe/trunk/test/CodeGen/avx512vl-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512vl-builtins.c?rev=286757&r1=286756&r2=286757&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/avx512vl-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx512vl-builtins.c Sun Nov 13 01:26:34 2016
@@ -4285,37 +4285,41 @@ __m256i test_mm256_maskz_srav_epi32(__mm
__m128i test_mm_srav_epi64(__m128i __X, __m128i __Y) {
// CHECK-LABEL: @test_mm_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.128
+ // CHECK: @llvm.x86.avx512.psrav.q.128
return _mm_srav_epi64(__X, __Y);
}
__m128i test_mm_mask_srav_epi64(__m128i __W, __mmask8 __U, __m128i __X,
__m128i __Y) {
// CHECK-LABEL: @test_mm_mask_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.128
+ // CHECK: @llvm.x86.avx512.psrav.q.128
+ // CHECK: select <2 x i1> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}
return _mm_mask_srav_epi64(__W, __U, __X, __Y);
}
__m128i test_mm_maskz_srav_epi64(__mmask8 __U, __m128i __X, __m128i __Y) {
// CHECK-LABEL: @test_mm_maskz_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.128
+ // CHECK: @llvm.x86.avx512.psrav.q.128
+ // CHECK: select <2 x i1> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}
return _mm_maskz_srav_epi64(__U, __X, __Y);
}
__m256i test_mm256_srav_epi64(__m256i __X, __m256i __Y) {
// CHECK-LABEL: @test_mm256_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.256
+ // CHECK: @llvm.x86.avx512.psrav.q.256
return _mm256_srav_epi64(__X, __Y);
}
__m256i test_mm256_mask_srav_epi64(__m256i __W, __mmask8 __U, __m256i __X,
__m256i __Y) {
// CHECK-LABEL: @test_mm256_mask_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.256
+ // CHECK: @llvm.x86.avx512.psrav.q.256
+ // CHECK: select <4 x i1> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> %{{.*}}
return _mm256_mask_srav_epi64(__W, __U, __X, __Y);
}
__m256i test_mm256_maskz_srav_epi64(__mmask8 __U, __m256i __X, __m256i __Y) {
// CHECK-LABEL: @test_mm256_maskz_srav_epi64
- // CHECK: @llvm.x86.avx512.mask.psrav.q.256
+ // CHECK: @llvm.x86.avx512.psrav.q.256
+ // CHECK: select <4 x i1> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> %{{.*}}
return _mm256_maskz_srav_epi64(__U, __X, __Y);
}
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
