https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 0ea3b2be9d364a042c7e7114b0f72fc3c144d2a0 Mon Sep 17 00:00:00 2001
From: YunQiang Su <s...@gcc.gnu.org>
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then
LLVM meet an internal error.
'r' is rejected by LLVM by:
couldn't allocate input reg for constraint 'r'
Fixes: #64241
---
clang/lib/Basic/Targets/Mips.h | 3 +++
.../CodeGen/Mips/inline-asm-constraints.c | 18 +++++++++++++
clang/test/Sema/inline-asm-validate-mips.c | 8 ++++++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +++++---
.../Mips/inlineasm-constraints-softfloat.ll | 25 +++++++++++++++++++
5 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..2b8ad6645e605f 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -238,6 +238,9 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
+ if (*Name == 'f' && FloatABI == SoftFloat)
+ return false;
+ LLVM_FALLTHROUGH;
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00000000000000..0a4cb0b34570e6
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN: -DSOFT_FLOAT_CONSTRAINT_R \
+// RUN: -DFLOAT=float -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_SINGLE
+
+// RUN: %clang_cc1 %s -triple mips -target-feature +soft-float \
+// RUN: -DSOFT_FLOAT_CONSTRAINT_R \
+// RUN: -DFLOAT=double -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix SOFT_FLOAT_CONSTRAINT_R_DOUBLE
+
+#ifdef SOFT_FLOAT_CONSTRAINT_R
+// SOFT_FLOAT_CONSTRAINT_R_SINGLE: call void asm sideeffect "",
"r,~{$1}"(float %2) #1, !srcloc !2
+// SOFT_FLOAT_CONSTRAINT_R_DOUBLE: call void asm sideeffect "",
"r,~{$1}"(double %2) #1, !srcloc !2
+void read_float(FLOAT* p) {
+ FLOAT result = *p;
+ __asm__("" ::"r"(result));
+}
+#endif // SOFT_FLOAT_CONSTRAINT_R
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00000000000000..5a123cc5fa79c3
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float p) {
+ float result = p;
+ __asm__("" ::"f"(result)); // expected-error{{invalid input constraint 'f'
in asm}}
+}
+#endif // SOFT_FLOAT_NO_CONSTRAINT_F
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index b2812f87914df7..97e830cec27cad 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
new file mode 100644
index 00000000000000..7e0b7a0c33b55f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
@@ -0,0 +1,25 @@
+; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+
+define dso_local void @read_double(ptr nocapture noundef readonly %0)
local_unnamed_addr #0 {
+ %2 = load double, ptr %0, align 8
+; MIPS32-LABEL: read_double:
+; MIPS32: lw $2, 4($4)
+; MIPS32-NEXT: lw $3, 0($4)
+; MIPS64-LABEL: read_double:
+; MIPS64: ld $2, 0($4)
+ tail call void asm sideeffect "", "r,~{$1}"(double %2)
+ ret void
+}
+
+define dso_local void @read_float(ptr nocapture noundef readonly %0)
local_unnamed_addr #0 {
+ %2 = load float, ptr %0, align 8
+; MIPS32-LABEL: read_float:
+; MIPS32: lw $2, 0($4)
+; MIPS64-LABEL: read_float:
+; MIPS64: lw $2, 0($4)
+ tail call void asm sideeffect "", "r,~{$1}"(float %2)
+ ret void
+}
+
+attributes #0 = { "target-features"="+soft-float" "use-soft-float"="true" }
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