llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Alexandros Lamprineas (labrinea) <details> <summary>Changes</summary> This patch follows the latest ACLE spec (see PR #<!-- -->279). It adds a name alias for FEAT_RDM and adjusts priorities for FEAT_DOTPROD, FEAT_SM4, FEAT_FP16FML, FEAT_RDM. --- Full diff: https://github.com/llvm/llvm-project/pull/79316.diff 5 Files Affected: - (modified) clang/test/CodeGen/attr-target-version.c (+19-2) - (modified) clang/test/Sema/attr-target-clones-aarch64.c (+1-1) - (modified) clang/test/SemaCXX/attr-target-version.cpp (+1) - (modified) llvm/include/llvm/TargetParser/AArch64TargetParser.h (+11-8) - (modified) llvm/lib/TargetParser/AArch64TargetParser.cpp (+13-2) ``````````diff diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c index 89279852a8c91d..8d53a073b37cbe 100644 --- a/clang/test/CodeGen/attr-target-version.c +++ b/clang/test/CodeGen/attr-target-version.c @@ -36,6 +36,7 @@ inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void inline int __attribute__((target_version("sve2+sve2-pmull128+sve2-bitperm"))) fmv_inline(void) { return 9; } inline int __attribute__((target_version("sve2-sm4+memtag2"))) fmv_inline(void) { return 10; } inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void) { return 11; } +inline int __attribute__((target_version("rdma+sm4"))) fmv_inline(void) { return 12; } inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; } __attribute__((target_version("ls64"))) int fmv_e(void); @@ -359,6 +360,14 @@ int hoo(void) { // CHECK: resolver_return21: // CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt // CHECK: resolver_else22: +// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 96 +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 96 +// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] +// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] +// CHECK: resolver_return23: +// CHECK-NEXT: ret ptr @fmv_inline._Msm4Mrdma +// CHECK: resolver_else24: // CHECK-NEXT: ret ptr @fmv_inline.default // // @@ -616,6 +625,13 @@ int hoo(void) { // // // CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msm4Mrdma +// CHECK-SAME: () #[[ATTR24:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 12 +// +// +// CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline.default // CHECK-SAME: () #[[ATTR2]] { // CHECK-NEXT: entry: @@ -624,7 +640,7 @@ int hoo(void) { // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb -// CHECK-SAME: () #[[ATTR24:[0-9]+]] { +// CHECK-SAME: () #[[ATTR25:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -769,7 +785,8 @@ int hoo(void) { // CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm" } // CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+mte,+neon,+sve,+sve2,+sve2-sm4" } // CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+mops,+mte,+rcpc,+rcpc3" } -// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+sb" } +// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon,+rdm,+sm4" } +// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+sb" } //. // CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } // CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c index 4054b7c837ec99..0ce277f41884c6 100644 --- a/clang/test/Sema/attr-target-clones-aarch64.c +++ b/clang/test/Sema/attr-target-clones-aarch64.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple aarch64-linux-gnu -fsyntax-only -verify %s -void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops"))) no_def(void); +void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops", "rdma"))) no_def(void); // expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}} void __attribute__((target_clones("default+sha3"))) warn1(void); diff --git a/clang/test/SemaCXX/attr-target-version.cpp b/clang/test/SemaCXX/attr-target-version.cpp index 5c542ad2e2dcab..0bd710c4e282ad 100644 --- a/clang/test/SemaCXX/attr-target-version.cpp +++ b/clang/test/SemaCXX/attr-target-version.cpp @@ -7,6 +7,7 @@ void __attribute__((target_version("dotprod"))) no_def(void); void __attribute__((target_version("rdm+fp"))) no_def(void); void __attribute__((target_version("rcpc3"))) no_def(void); void __attribute__((target_version("mops"))) no_def(void); +void __attribute__((target_version("rdma"))) no_def(void); // expected-error@+1 {{no matching function for call to 'no_def'}} void foo(void) { no_def(); } diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 623fdc21ba65a6..cc30cc92f239ea 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -222,7 +222,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0}, {"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260}, {"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180}, - {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 50}, + {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 104}, {"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190}, {"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200}, {"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290}, @@ -233,7 +233,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30}, {"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP, "+fp-armv8,+neon", 90}, {"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16, "+fullfp16,+fp-armv8,+neon", 170}, - {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 40}, + {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 175}, {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250}, {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0}, {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270}, @@ -259,7 +259,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230}, {"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240}, {"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3, "+rcpc,+rcpc3", 241}, - {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 70}, + {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 108}, {"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10}, {"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300}, {"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470}, @@ -267,7 +267,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2, "+sha2,+fp-armv8,+neon", 130}, {"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140}, {"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100}, - {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 60}, + {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 106}, {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "", 0}, {"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560}, {"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570}, @@ -807,13 +807,15 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))}, }; -// An alias for a CPU. -struct CpuAlias { - StringRef Alias; +// Name alias +struct Alias { + StringRef AltName; StringRef Name; }; -inline constexpr CpuAlias CpuAliases[] = {{"grace", "neoverse-v2"}}; +inline constexpr Alias CpuAliases[] = {{"grace", "neoverse-v2"}}; + +inline constexpr Alias ExtAliases[] = {{"rdma", "rdm"}}; bool getExtensionFeatures( const AArch64::ExtensionBitset &Extensions, @@ -821,6 +823,7 @@ bool getExtensionFeatures( StringRef getArchExtFeature(StringRef ArchExt); StringRef resolveCPUAlias(StringRef CPU); +StringRef resolveExtAlias(StringRef ArchExt); // Information by Name const ArchInfo *getArchForCpu(StringRef CPU); diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index fd47f786a46ef4..825f6633719d55 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -69,7 +69,14 @@ bool AArch64::getExtensionFeatures( StringRef AArch64::resolveCPUAlias(StringRef Name) { for (const auto &A : CpuAliases) - if (A.Alias == Name) + if (A.AltName == Name) + return A.Name; + return Name; +} + +StringRef AArch64::resolveExtAlias(StringRef Name) { + for (const auto &A : ExtAliases) + if (A.AltName == Name) return A.Name; return Name; } @@ -91,7 +98,7 @@ void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) { Values.push_back(C.Name); for (const auto &Alias : CpuAliases) - Values.push_back(Alias.Alias); + Values.push_back(Alias.AltName); } bool AArch64::isX18ReservedByDefault(const Triple &TT) { @@ -114,6 +121,10 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) { } std::optional<AArch64::ExtensionInfo> AArch64::parseArchExtension(StringRef ArchExt) { + // Resolve aliases first. + ArchExt = resolveExtAlias(ArchExt); + + // Then find the Extension name. for (const auto &A : Extensions) { if (ArchExt == A.Name) return A; `````````` </details> https://github.com/llvm/llvm-project/pull/79316 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
