Author: Craig Topper Date: 2023-12-28T18:15:12-08:00 New Revision: 2dc50d28414c827b6723ae6b01c20a7fc3f38165
URL: https://github.com/llvm/llvm-project/commit/2dc50d28414c827b6723ae6b01c20a7fc3f38165 DIFF: https://github.com/llvm/llvm-project/commit/2dc50d28414c827b6723ae6b01c20a7fc3f38165.diff LOG: [RISCV] Correct the CHECK prefixes in attr-riscv-rvv-vector-bits-globals.c to use the correct vector size. NFC These were copied from AArch64 where vscale is multiplied by 128 to get the vector length. For RISC-V, vscale is multiplied by 64. Added: Modified: clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c index 447c3803dec8e3..8bdcd9af20efca 100644 --- a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c +++ b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 -S -O1 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128 -// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -S -O1 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512 +// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 -S -O1 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-64 +// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -S -O1 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256 // REQUIRES: riscv-registered-target @@ -25,17 +25,17 @@ fixed_int64m1_t global_i64; // WRITES //===----------------------------------------------------------------------===// -// CHECK-128-LABEL: @write_global_i64( -// CHECK-128-NEXT: entry: -// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <1 x i64> @llvm.vector.extract.v1i64.nxv1i64(<vscale x 1 x i64> [[V:%.*]], i64 0) -// CHECK-128-NEXT: store <1 x i64> [[CASTFIXEDSVE]], ptr @global_i64, align 8, !tbaa [[TBAA4:![0-9]+]] -// CHECK-128-NEXT: ret void +// CHECK-64-LABEL: @write_global_i64( +// CHECK-64-NEXT: entry: +// CHECK-64-NEXT: [[CAST_FIXED:%.*]] = tail call <1 x i64> @llvm.vector.extract.v1i64.nxv1i64(<vscale x 1 x i64> [[V:%.*]], i64 0) +// CHECK-64-NEXT: store <1 x i64> [[CAST_FIXED]], ptr @global_i64, align 8, !tbaa [[TBAA4:![0-9]+]] +// CHECK-64-NEXT: ret void // -// CHECK-512-LABEL: @write_global_i64( -// CHECK-512-NEXT: entry: -// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[V:%.*]], i64 0) -// CHECK-512-NEXT: store <4 x i64> [[CASTFIXEDSVE]], ptr @global_i64, align 8, !tbaa [[TBAA4:![0-9]+]] -// CHECK-512-NEXT: ret void +// CHECK-256-LABEL: @write_global_i64( +// CHECK-256-NEXT: entry: +// CHECK-256-NEXT: [[CAST_FIXED:%.*]] = tail call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> [[V:%.*]], i64 0) +// CHECK-256-NEXT: store <4 x i64> [[CAST_FIXED]], ptr @global_i64, align 8, !tbaa [[TBAA4:![0-9]+]] +// CHECK-256-NEXT: ret void // void write_global_i64(vint64m1_t v) { global_i64 = v; } @@ -43,16 +43,16 @@ void write_global_i64(vint64m1_t v) { global_i64 = v; } // READS //===----------------------------------------------------------------------===// -// CHECK-128-LABEL: @read_global_i64( -// CHECK-128-NEXT: entry: -// CHECK-128-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr @global_i64, align 8, !tbaa [[TBAA4]] -// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = tail call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v1i64(<vscale x 1 x i64> undef, <1 x i64> [[TMP0]], i64 0) -// CHECK-128-NEXT: ret <vscale x 1 x i64> [[CASTSCALABLESVE]] +// CHECK-64-LABEL: @read_global_i64( +// CHECK-64-NEXT: entry: +// CHECK-64-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr @global_i64, align 8, !tbaa [[TBAA4]] +// CHECK-64-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v1i64(<vscale x 1 x i64> undef, <1 x i64> [[TMP0]], i64 0) +// CHECK-64-NEXT: ret <vscale x 1 x i64> [[CAST_SCALABLE]] // -// CHECK-512-LABEL: @read_global_i64( -// CHECK-512-NEXT: entry: -// CHECK-512-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @global_i64, align 8, !tbaa [[TBAA4]] -// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = tail call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> undef, <4 x i64> [[TMP0]], i64 0) -// CHECK-512-NEXT: ret <vscale x 1 x i64> [[CASTSCALABLESVE]] +// CHECK-256-LABEL: @read_global_i64( +// CHECK-256-NEXT: entry: +// CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @global_i64, align 8, !tbaa [[TBAA4]] +// CHECK-256-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> undef, <4 x i64> [[TMP0]], i64 0) +// CHECK-256-NEXT: ret <vscale x 1 x i64> [[CAST_SCALABLE]] // vint64m1_t read_global_i64() { return global_i64; } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
