llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-x86 Author: David Li (david-xl) <details> <summary>Changes</summary> Depositing value into the lowest byte/word is a common code pattern. This patch improves the code generation for it to avoid redundant AND and OR operations. --- Full diff: https://github.com/llvm/llvm-project/pull/75978.diff 2 Files Affected: - (modified) llvm/lib/Target/X86/X86InstrMisc.td (+10) - (added) llvm/test/CodeGen/X86/insert.ll (+35) ``````````diff diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 2ea10e317e12b4..f9ae88a8fa8ae8 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), + (i64 (zextloadi8 addr:$src))), + (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit) +>; + +def : Pat<(or (and GR64:$dst, -65536), + (i64 (zextloadi16 addr:$src))), + (INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit) +>; + let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", diff --git a/llvm/test/CodeGen/X86/insert.ll b/llvm/test/CodeGen/X86/insert.ll new file mode 100644 index 00000000000000..30b0bca8c63bfe --- /dev/null +++ b/llvm/test/CodeGen/X86/insert.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 + +define i64 @sub8(i64 noundef %res, ptr %byte) { +; X64-LABEL: sub8: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movb (%rsi), %al +; X64-NEXT: retq +entry: + %and = and i64 %res, -256 + %d = load i8, ptr %byte, align 1 + %conv2 = zext i8 %d to i64 + %or = or i64 %and, %conv2 + ret i64 %or +} + + +define i64 @sub16(i64 noundef %res, ptr %byte) { +; X64-LABEL: sub16: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movw (%rsi), %ax +; X64-NEXT: retq +entry: + %and = and i64 %res, -65536 + %d = load i16, ptr %byte, align 1 + %conv2 = zext i16 %d to i64 + %or = or i64 %and, %conv2 + ret i64 %or +} + + + + `````````` </details> https://github.com/llvm/llvm-project/pull/75978 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
