Author: Jianjian Guan Date: 2023-12-15T11:16:05+08:00 New Revision: 3fe81410b23c4f13954e99c7180fa8a7e1e8ee88
URL: https://github.com/llvm/llvm-project/commit/3fe81410b23c4f13954e99c7180fa8a7e1e8ee88 DIFF: https://github.com/llvm/llvm-project/commit/3fe81410b23c4f13954e99c7180fa8a7e1e8ee88.diff LOG: [clang][RISCV] Change default abi with f extension but without d extension (#73489) Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f and not d, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. Added: Modified: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-abi.c clang/test/Driver/riscv-cpus.c llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll llvm/test/CodeGen/RISCV/calling-conv-half.ll llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll llvm/test/CodeGen/RISCV/float-frem.ll llvm/test/CodeGen/RISCV/float-select-verify.ll llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll llvm/test/CodeGen/RISCV/half-fcmp.ll Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 066e4ac5b9e54b..f5ae6bb8925202 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -968,6 +968,9 @@ RISC-V Support - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f + for RV64. + CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e5..16568271564c79 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d49..d7fa7c9854a48f 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s @@ -178,7 +178,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E76: "-target-feature" "+c" // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E76: "-target-abi" "ilp32" +// MCPU-SIFIVE-E76: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index bef812b0b12096..1dd853259c0472 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -140,6 +140,7 @@ Changes to the RISC-V Backend * The Zfa extension version was upgraded to 1.0 and is no longer experimental. * Zihintntl extension version was upgraded to 1.0 and is no longer experimental. * Intrinsics were added for Zk*, Zbb, and Zbc. See https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#scalar-bit-manipulation-extension-intrinsics +* Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 85c34dd6206307..aad7ab8361af96 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -1292,12 +1292,16 @@ StringRef RISCVISAInfo::computeDefaultABI() const { if (XLen == 32) { if (hasExtension("d")) return "ilp32d"; + if (hasExtension("f")) + return "ilp32f"; if (hasExtension("e")) return "ilp32e"; return "ilp32"; } else if (XLen == 64) { if (hasExtension("d")) return "lp64d"; + if (hasExtension("f")) + return "lp64f"; if (hasExtension("e")) return "lp64e"; return "lp64"; diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll index 7111316931f19b..1aa7783fedd2ae 100644 --- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32 -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32F diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll index 6587f0c8c5af7b..ad4578bda344d2 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF +; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F ; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN diff --git a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll index 3916bcdc61da4c..a74f7bbe2331b2 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IF ; Exercises the ILP32 calling convention code in the case that f32 is a legal diff --git a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll index 19a5d9ca03c6ae..8ebe9b6301c44d 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64 %s ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64LP64F %s diff --git a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll index 3324d366cf0e47..2495b1ad300c6d 100644 --- a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfinx -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IZFINX %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s -; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfinx -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IZFINX %s ; This file tests cases where simple floating point operations can be diff --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll index cb80c6cfbeaa06..6c15da0cca7bf7 100644 --- a/llvm/test/CodeGen/RISCV/float-frem.ll +++ b/llvm/test/CodeGen/RISCV/float-frem.ll @@ -19,12 +19,7 @@ define float @frem_f32(float %a, float %b) nounwind { ; ; RV64IF-LABEL: frem_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IF-NEXT: call fmodf@plt -; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IF-NEXT: addi sp, sp, 16 -; RV64IF-NEXT: ret +; RV64IF-NEXT: tail fmodf@plt ; ; RV32IZFINX-LABEL: frem_f32: ; RV32IZFINX: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-select-verify.ll b/llvm/test/CodeGen/RISCV/float-select-verify.ll index 802225ff9ac984..6f414f16163b63 100644 --- a/llvm/test/CodeGen/RISCV/float-select-verify.ll +++ b/llvm/test/CodeGen/RISCV/float-select-verify.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -stop-after=finalize-isel < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -stop-after=finalize-isel < %s | FileCheck %s define dso_local void @buz(i1 %pred, float %a, float %b) { ; CHECK-LABEL: name: buz diff --git a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll index db35a55e9f59fc..a103a9e09d1498 100644 --- a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll @@ -1,25 +1,25 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s -; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IZHINX %s -; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IZHINX %s -; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IZFHMIN %s -; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IZFHMIN %s -; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs \ ; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV32IZHINXMIN %s -; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs \ ; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV64IZHINXMIN %s ; This file tests cases where simple floating point operations can be diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll index a709c06f6776e8..81ef56635eebcf 100644 --- a/llvm/test/CodeGen/RISCV/half-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll @@ -8,17 +8,17 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ ; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV32I %s +; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV64I %s +; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s +; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s +; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \ ; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
