https://github.com/dtemirbulatov updated
https://github.com/llvm/llvm-project/pull/72827
>From ae1b183325c08ec8eb1cb82977591563410c0361 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <dinar.temirbula...@arm.com>
Date: Mon, 20 Nov 2023 07:04:18 +0000
Subject: [PATCH 1/5] [AArch64][SME2] Add PEXT, PSEL builtins for SME2
This change enables PEXT, PSEL builtins for SME2 target.
---
clang/include/clang/Basic/arm_sve.td | 30 +--
.../acle_sve2p1_pext.c | 207 +++++++++++++++++-
.../acle_sve2p1_psel.c | 5 +
3 files changed, 218 insertions(+), 24 deletions(-)
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 85656c00c5b3e..acba13bcc14c5 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1935,16 +1935,25 @@ def SVBGRP : SInst<"svbgrp[_{d}]", "ddd",
"UcUsUiUl", MergeNone, "aarch64_sv
def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone,
"aarch64_sve_bgrp_x">;
}
-let TargetGuard = "sve2p1" in {
-def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone,
"aarch64_sve_fclamp", [], []>;
+let TargetGuard = "sve2p1|sme" in {
+def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc", MergeNone, "",
[IsStreamingCompatible], []>;
+def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "",
[IsStreamingCompatible], []>;
+def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "",
[IsStreamingCompatible], []>;
+def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "",
[IsStreamingCompatible], []>;
+}
-def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
-def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
+let TargetGuard = "sve2p1|sme2" in {
+def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone,
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone,
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone,
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone,
"", [IsStreamingCompatible], []>;
-def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone,
"", [], []>;
-def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone,
"", [], []>;
-def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone,
"", [], []>;
-def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone,
"", [], []>;
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1,
ImmCheck0_1>]>;
+}
+
+let TargetGuard = "sve2p1" in {
+def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone,
"aarch64_sve_fclamp", [], []>;
def SVWHILEGE_COUNT : SInst<"svwhilege_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}", "}lli", "QcQsQiQl", MergeNone,
"aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
@@ -2045,11 +2054,6 @@ let TargetGuard = "sve2p1" in {
def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil", MergeNone,
"aarch64_sve_sclamp", [], []>;
def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone,
"aarch64_sve_uclamp", [], []>;
-def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc", MergeNone, "", [], []>;
-def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [], []>;
-def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>;
-def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
-
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index fe15d5a9db81f..76603e384b99c 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -1,10 +1,17 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x
c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall
-o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sve2p1 -S -DIGNORE_STREAMING_ATTR -disable-O0-optnone -Werror
-Wall -o /dev/null %s
#include <arm_sve.h>
+#ifdef IGNORE_STREAMING_ATTR
+#define __attribute__(...)
+#endif
+
// CHECK-LABEL: @test_svpext_lane_c8_0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
@@ -15,7 +22,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_0(svcount_t c) {
+svbool_t test_svpext_lane_c8_0(svcount_t c) __arm_streaming {
return svpext_lane_c8(c, 0);
}
@@ -29,7 +36,7 @@ svbool_t test_svpext_lane_c8_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 3)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_3(svcount_t c) {
+svbool_t test_svpext_lane_c8_3(svcount_t c) __arm_streaming {
return svpext_lane_c8(c, 3);
}
@@ -45,7 +52,7 @@ svbool_t test_svpext_lane_c8_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_0(svcount_t c) {
+svbool_t test_svpext_lane_c16_0(svcount_t c) __arm_streaming {
return svpext_lane_c16(c, 0);
}
@@ -61,7 +68,7 @@ svbool_t test_svpext_lane_c16_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_3(svcount_t c) {
+svbool_t test_svpext_lane_c16_3(svcount_t c) __arm_streaming {
return svpext_lane_c16(c, 3);
}
@@ -77,7 +84,7 @@ svbool_t test_svpext_lane_c16_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_0(svcount_t c) {
+svbool_t test_svpext_lane_c32_0(svcount_t c) __arm_streaming {
return svpext_lane_c32(c, 0);
}
@@ -93,7 +100,7 @@ svbool_t test_svpext_lane_c32_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_3(svcount_t c) {
+svbool_t test_svpext_lane_c32_3(svcount_t c) __arm_streaming {
return svpext_lane_c32(c, 3);
}
@@ -109,7 +116,7 @@ svbool_t test_svpext_lane_c32_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_0(svcount_t c) {
+svbool_t test_svpext_lane_c64_0(svcount_t c) __arm_streaming {
return svpext_lane_c64(c, 0);
}
@@ -125,7 +132,7 @@ svbool_t test_svpext_lane_c64_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_3(svcount_t c) {
+svbool_t test_svpext_lane_c64_3(svcount_t c) __arm_streaming {
return svpext_lane_c64(c, 3);
}
@@ -147,6 +154,184 @@ svbool_t test_svpext_lane_c64_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
//
-svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) __arm_streaming {
return svpext_lane_c8_x2(c, 0);
}
+
+// CHECK-LABEL: @test_svpext_lane_c8_x2_1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i1>, <vscale x 16
x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") [[C:%.*]],
i32 1)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x
16 x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP1]], i64 0)
+// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x
16 x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z24test_svpext_lane_c8_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i1>, <vscale x
16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount")
[[C:%.*]], i32 1)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i1>,
<vscale x 16 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i1>,
<vscale x 16 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
+//
+svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) __arm_streaming {
+ return svpext_lane_c8_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c16_x2_0(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x
i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32
0)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c16_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x
8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]],
i32 0)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale
x 8 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale
x 8 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) __arm_streaming {
+ return svpext_lane_c16_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c16_x2_1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x
i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32
1)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c16_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x
8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]],
i32 1)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale
x 8 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale
x 8 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) __arm_streaming {
+ return svpext_lane_c16_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c32_x2_0(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x
i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32
0)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c32_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x
4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]],
i32 0)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale
x 4 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale
x 4 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) __arm_streaming {
+ return svpext_lane_c32_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c32_x2_1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x
i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32
1)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c32_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x
4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]],
i32 1)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale
x 4 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale
x 4 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) __arm_streaming {
+ return svpext_lane_c32_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c64_x2_0(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x
i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32
0)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c64_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x
2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]],
i32 0)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale
x 2 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale
x 2 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) __arm_streaming {
+ return svpext_lane_c64_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c64_x2_1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x
i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32
1)
+// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2
x i1> } [[TMP0]], 0
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2
x i1> } [[TMP0]], 1
+// CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c64_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x
2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]],
i32 1)
+// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale
x 2 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x
i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale
x 2 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) __arm_streaming {
+ return svpext_lane_c64_x2(c, 1);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
index aa2a35c2fd254..9b753553877ab 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
@@ -5,6 +5,11 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
+// RUN: -target-feature +sve -target-feature +sme2 -S -O1 -Werror -emit-llvm
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
+// RUN: -target-feature +sve -target-feature +sme2 -S -O1 -Werror -emit-llvm
-o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall
-o /dev/null %s
#include <arm_sve.h>
>From fe412612653048e6557afdf4790a908bcbefcc3a Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <dinar.temirbula...@arm.com>
Date: Wed, 6 Dec 2023 15:39:38 +0000
Subject: [PATCH 2/5] Fixed remarks.
---
clang/include/clang/Basic/arm_sve.td | 9 ++--
clang/include/clang/Basic/arm_sve_sme_incl.td | 1 +
.../acle_sve2p1_pext.c | 44 +++++++++----------
.../acle_sve2p1_psel.c | 22 +++++-----
4 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index acba13bcc14c5..a0f0da7542373 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1940,16 +1940,15 @@ def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc",
MergeNone, "", [IsStreamin
def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "",
[IsStreamingCompatible], []>;
def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "",
[IsStreamingCompatible], []>;
def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "",
[IsStreamingCompatible], []>;
-}
-
-let TargetGuard = "sve2p1|sme2" in {
def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone,
"", [IsStreamingCompatible], []>;
def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone,
"", [IsStreamingCompatible], []>;
def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone,
"", [IsStreamingCompatible], []>;
def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone,
"", [IsStreamingCompatible], []>;
+}
-def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
-def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1,
ImmCheck0_1>]>;
+let TargetGuard = "sve2p1|sme2" in {
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingOrSVE2p1], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingOrSVE2p1], [ImmCheck<1,
ImmCheck0_1>]>;
}
let TargetGuard = "sve2p1" in {
diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index 040ce95a57de3..161d3b2b9ab9b 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -225,6 +225,7 @@ def IsSharedZA : FlagType<0x8000000000>;
def IsPreservesZA : FlagType<0x10000000000>;
def IsReadZA : FlagType<0x20000000000>;
def IsWriteZA : FlagType<0x40000000000>;
+def IsStreamingOrSVE2p1 : FlagType<0x80000000000>; // Use for intrinsics
that are common between sme/sme2 and sve2p1.
// These must be kept in sync with the flags in
include/clang/Basic/TargetBuiltins.h
class ImmCheckType<int val> {
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index 76603e384b99c..d76ebe630fe87 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -1,17 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x
c++ %s | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall
-o /dev/null %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sve2p1 -S -DIGNORE_STREAMING_ATTR -disable-O0-optnone -Werror
-Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
#include <arm_sve.h>
-#ifdef IGNORE_STREAMING_ATTR
-#define __attribute__(...)
-#endif
-
// CHECK-LABEL: @test_svpext_lane_c8_0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
@@ -22,7 +18,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_0(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c8_0(svcount_t c) {
return svpext_lane_c8(c, 0);
}
@@ -36,7 +32,7 @@ svbool_t test_svpext_lane_c8_0(svcount_t c) __arm_streaming {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 3)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_3(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c8_3(svcount_t c) {
return svpext_lane_c8(c, 3);
}
@@ -52,7 +48,7 @@ svbool_t test_svpext_lane_c8_3(svcount_t c) __arm_streaming {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_0(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c16_0(svcount_t c) {
return svpext_lane_c16(c, 0);
}
@@ -68,7 +64,7 @@ svbool_t test_svpext_lane_c16_0(svcount_t c) __arm_streaming {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_3(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c16_3(svcount_t c) {
return svpext_lane_c16(c, 3);
}
@@ -84,7 +80,7 @@ svbool_t test_svpext_lane_c16_3(svcount_t c) __arm_streaming {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_0(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c32_0(svcount_t c) {
return svpext_lane_c32(c, 0);
}
@@ -100,7 +96,7 @@ svbool_t test_svpext_lane_c32_0(svcount_t c) __arm_streaming
{
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_3(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c32_3(svcount_t c) {
return svpext_lane_c32(c, 3);
}
@@ -116,7 +112,7 @@ svbool_t test_svpext_lane_c32_3(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_0(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c64_0(svcount_t c) {
return svpext_lane_c64(c, 0);
}
@@ -132,7 +128,7 @@ svbool_t test_svpext_lane_c64_0(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_3(svcount_t c) __arm_streaming {
+svbool_t test_svpext_lane_c64_3(svcount_t c) {
return svpext_lane_c64(c, 3);
}
@@ -154,7 +150,7 @@ svbool_t test_svpext_lane_c64_3(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
//
-svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) {
return svpext_lane_c8_x2(c, 0);
}
@@ -176,7 +172,7 @@ svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
//
-svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) {
return svpext_lane_c8_x2(c, 1);
}
@@ -202,7 +198,7 @@ svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) {
return svpext_lane_c16_x2(c, 0);
}
@@ -228,7 +224,7 @@ svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) {
return svpext_lane_c16_x2(c, 1);
}
@@ -254,7 +250,7 @@ svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) {
return svpext_lane_c32_x2(c, 0);
}
@@ -280,7 +276,7 @@ svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) {
return svpext_lane_c32_x2(c, 1);
}
@@ -306,7 +302,7 @@ svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) {
return svpext_lane_c64_x2(c, 0);
}
@@ -332,6 +328,6 @@ svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c)
__arm_streaming {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) __arm_streaming {
+svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) {
return svpext_lane_c64_x2(c, 1);
}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
index 9b753553877ab..73b7b0347dd97 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
@@ -6,10 +6,10 @@
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
-// RUN: -target-feature +sve -target-feature +sme2 -S -O1 -Werror -emit-llvm
-o - %s | FileCheck %s
+// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s |
FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
-// RUN: -target-feature +sve -target-feature +sme2 -S -O1 -Werror -emit-llvm
-o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall
-o /dev/null %s
+// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
#include <arm_sve.h>
@@ -25,7 +25,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 16 x
i1> [[P2:%.*]], i32 [[ADD]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_b8(p1, p2, idx + 15);
}
@@ -43,7 +43,7 @@ svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 8 x i1>
[[TMP0]], i32 [[ADD]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_b16(p1, p2, idx + 7);
}
@@ -61,7 +61,7 @@ svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 4 x i1>
[[TMP0]], i32 [[ADD]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_b32(p1, p2, idx + 3);
}
@@ -79,7 +79,7 @@ svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 2 x i1>
[[TMP0]], i32 [[ADD]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_b64(p1, p2, idx + 1);
}
@@ -99,7 +99,7 @@ svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
[[TMP1]])
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP2]]
//
-svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_c8(p1, p2, idx + 15);
}
@@ -121,7 +121,7 @@ svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
[[TMP2]])
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
//
-svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_c16(p1, p2, idx + 7);
}
@@ -143,7 +143,7 @@ svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
[[TMP2]])
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
//
-svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_c32(p1, p2, idx + 3);
}
@@ -165,6 +165,6 @@ svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2,
uint32_t idx) {
// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
[[TMP2]])
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
//
-svcount_t test_svpsel_lane_c64(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c64(svcount_t p1, svbool_t p2, uint32_t idx)
__arm_streaming_compatible {
return svpsel_lane_c64(p1, p2, idx + 1);
}
>From 34f1c31c008d6a270e8d5c239026c47518dbf0f9 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <dinar.temirbula...@arm.com>
Date: Thu, 7 Dec 2023 15:55:54 +0000
Subject: [PATCH 3/5] Temporory removed IsStreamingOrSVE2p1.
---
clang/include/clang/Basic/arm_sve.td | 5 +++--
clang/include/clang/Basic/arm_sve_sme_incl.td | 1 -
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index a0f0da7542373..42ad7da737b49 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1947,8 +1947,9 @@ def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64",
"}}Pm", "Pl", MergeNone, "",
}
let TargetGuard = "sve2p1|sme2" in {
-def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingOrSVE2p1], [ImmCheck<1, ImmCheck0_3>]>;
-def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingOrSVE2p1], [ImmCheck<1,
ImmCheck0_1>]>;
+//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1,
ImmCheck0_1>]>;
}
let TargetGuard = "sve2p1" in {
diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index 161d3b2b9ab9b..040ce95a57de3 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -225,7 +225,6 @@ def IsSharedZA : FlagType<0x8000000000>;
def IsPreservesZA : FlagType<0x10000000000>;
def IsReadZA : FlagType<0x20000000000>;
def IsWriteZA : FlagType<0x40000000000>;
-def IsStreamingOrSVE2p1 : FlagType<0x80000000000>; // Use for intrinsics
that are common between sme/sme2 and sve2p1.
// These must be kept in sync with the flags in
include/clang/Basic/TargetBuiltins.h
class ImmCheckType<int val> {
>From 3f13dd27dd50e02619aa048297e87e15f7ba00c8 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <dinar.temirbula...@arm.com>
Date: Fri, 8 Dec 2023 13:45:32 +0000
Subject: [PATCH 4/5] Added __arm_streaming attribute in acle_sve2p1_pext.c
test for sve2p1 target.
---
.../acle_sve2p1_pext.c | 46 +++++++++++--------
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index d76ebe630fe87..05bc993a5cf44 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -1,13 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck
%s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
#include <arm_sve.h>
+#ifndef TEST_SME2
+#define ATTR
+#else
+#define ATTR __arm_streaming
+#endif
+
// CHECK-LABEL: @test_svpext_lane_c8_0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
@@ -18,7 +24,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_0(svcount_t c) {
+svbool_t test_svpext_lane_c8_0(svcount_t c) ATTR {
return svpext_lane_c8(c, 0);
}
@@ -32,7 +38,7 @@ svbool_t test_svpext_lane_c8_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 3)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
-svbool_t test_svpext_lane_c8_3(svcount_t c) {
+svbool_t test_svpext_lane_c8_3(svcount_t c) ATTR {
return svpext_lane_c8(c, 3);
}
@@ -48,7 +54,7 @@ svbool_t test_svpext_lane_c8_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_0(svcount_t c) {
+svbool_t test_svpext_lane_c16_0(svcount_t c) ATTR {
return svpext_lane_c16(c, 0);
}
@@ -64,7 +70,7 @@ svbool_t test_svpext_lane_c16_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c16_3(svcount_t c) {
+svbool_t test_svpext_lane_c16_3(svcount_t c) ATTR {
return svpext_lane_c16(c, 3);
}
@@ -80,7 +86,7 @@ svbool_t test_svpext_lane_c16_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_0(svcount_t c) {
+svbool_t test_svpext_lane_c32_0(svcount_t c) ATTR {
return svpext_lane_c32(c, 0);
}
@@ -96,7 +102,7 @@ svbool_t test_svpext_lane_c32_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c32_3(svcount_t c) {
+svbool_t test_svpext_lane_c32_3(svcount_t c) ATTR {
return svpext_lane_c32(c, 3);
}
@@ -112,7 +118,7 @@ svbool_t test_svpext_lane_c32_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_0(svcount_t c) {
+svbool_t test_svpext_lane_c64_0(svcount_t c) ATTR {
return svpext_lane_c64(c, 0);
}
@@ -128,7 +134,7 @@ svbool_t test_svpext_lane_c64_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1>
@llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
-svbool_t test_svpext_lane_c64_3(svcount_t c) {
+svbool_t test_svpext_lane_c64_3(svcount_t c) ATTR {
return svpext_lane_c64(c, 3);
}
@@ -150,7 +156,7 @@ svbool_t test_svpext_lane_c64_3(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
//
-svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) ATTR {
return svpext_lane_c8_x2(c, 0);
}
@@ -172,7 +178,7 @@ svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x
i1> [[TMP3]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP4]]
//
-svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) {
+svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) ATTR {
return svpext_lane_c8_x2(c, 1);
}
@@ -198,7 +204,7 @@ svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) ATTR {
return svpext_lane_c16_x2(c, 0);
}
@@ -224,7 +230,7 @@ svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) {
+svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) ATTR {
return svpext_lane_c16_x2(c, 1);
}
@@ -250,7 +256,7 @@ svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) ATTR {
return svpext_lane_c32_x2(c, 0);
}
@@ -276,7 +282,7 @@ svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) {
+svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) ATTR {
return svpext_lane_c32_x2(c, 1);
}
@@ -302,7 +308,7 @@ svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) ATTR {
return svpext_lane_c64_x2(c, 0);
}
@@ -328,6 +334,6 @@ svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) {
// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call <vscale x 32 x i1>
@llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x
i1> [[TMP5]], i64 16)
// CPP-CHECK-NEXT: ret <vscale x 32 x i1> [[TMP6]]
//
-svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) {
+svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) ATTR {
return svpext_lane_c64_x2(c, 1);
}
>From d90683dc350fba31d8939a4e677e1d53b1a51799 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <dinar.temirbula...@arm.com>
Date: Mon, 11 Dec 2023 14:07:27 +0000
Subject: [PATCH 5/5] Adjusting
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c test.
---
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index 05bc993a5cf44..a3206029019c3 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -2,8 +2,6 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck
%s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature
+sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
#include <arm_sve.h>
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