================
@@ -298,3 +298,11 @@ multiclass ZAAddSub<string n_suffix> {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// lookup table expand two contiguous registers
+//
+let TargetGuard = "sme2" in {
+ def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.dmdm",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2,
ImmCheck0_7>]>;
----------------
sdesmalen-arm wrote:
using `2.dmdm` doesn't seem right, as the specification requires a constant
`uint64_t` for `zt` and `imm_idx`. whereas `m` maps to `uint32_t` instead.
https://github.com/llvm/llvm-project/pull/73305
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