[llvm] [clang] [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (PR #72849)

[Sander de Smalen via cfe-commits]

================
@@ -326,9 +326,14 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
     return false;
   }
 
-  template <unsigned BaseReg> bool ImmToTile(SDValue N, SDValue &Imm) {
+  template <unsigned BaseReg, unsigned Max>
+  bool ImmToTile(SDValue N, SDValue &Imm) {
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sdesmalen-arm wrote:

If `ImmToTile` is now used for ZT, this is no longer the right name. Can you 
rename this to `ImmToReg` or something that like that instead?

https://github.com/llvm/llvm-project/pull/72849
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