Author: sstwcw Date: 2023-11-29T15:19:13Z New Revision: 9fa2d74be415a3e30d811c0acc05c45e1c55759e
URL: https://github.com/llvm/llvm-project/commit/9fa2d74be415a3e30d811c0acc05c45e1c55759e DIFF: https://github.com/llvm/llvm-project/commit/9fa2d74be415a3e30d811c0acc05c45e1c55759e.diff LOG: [clang-format] Indent Verilog case statements with comments (#71353) If a line contains a comment outside of (fake) parentheses, the part following it is indented according to `CurrentState.Indent`. A Verilog case label and the statement that follows are broken with mustBreakBefore. So the part that follows the case label needs some special handling. Previously, that variable was left out. So the indentation was wrong when there was a comment. old: ```Verilog case (data) 16'd0: result = // 10'b0111111111; endcase case (data) 16'd0: // // result = // 10'b0111111111; endcase ``` new: ```Verilog case (data) 16'd0: result = // 10'b0111111111; endcase case (data) 16'd0: // // result = // 10'b0111111111; endcase ``` Added: Modified: clang/lib/Format/ContinuationIndenter.cpp clang/unittests/Format/FormatTestVerilog.cpp Removed: ################################################################################ diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index 8fffdccd35c059b..4a10579255782b5 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -1208,8 +1208,10 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) { // Indentation of the statement following a Verilog case label is taken care // of in moveStateToNextToken. - if (Style.isVerilog() && Keywords.isVerilogEndOfLabel(Previous)) + if (Style.isVerilog() && PreviousNonComment && + Keywords.isVerilogEndOfLabel(*PreviousNonComment)) { return State.FirstIndent; + } if (Style.BreakBeforeBraces == FormatStyle::BS_Whitesmiths && State.Line->First->is(tok::kw_enum)) { @@ -1612,6 +1614,7 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, State.NextToken->MustBreakBefore && Keywords.isVerilogEndOfLabel(Current)) { State.FirstIndent += Style.IndentWidth; + CurrentState.Indent = State.FirstIndent; } unsigned Penalty = diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp index 6650caea80b0524..582887492f75967 100644 --- a/clang/unittests/Format/FormatTestVerilog.cpp +++ b/clang/unittests/Format/FormatTestVerilog.cpp @@ -344,6 +344,20 @@ TEST_F(FormatTestVerilog, Case) { " longfunction( //\n" " arg);\n" "endcase"); + verifyFormat("case (data)\n" + " 16'd0:\n" + " //\n" + " result = //\n" + " 10'b0111111111;\n" + "endcase"); + verifyFormat("case (data)\n" + " 16'd0:\n" + " //\n" + "\n" + " //\n" + " result = //\n" + " 10'b0111111111;\n" + "endcase"); Style = getDefaultStyle(); Style.ContinuationIndentWidth = 1; verifyFormat("case (data)\n" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
