https://github.com/TNorthover created https://github.com/llvm/llvm-project/pull/73499
These are still v8.6a and have no real changes as far as LLVM cares, so it's mostly just a copy/paste job (actually from https://github.com/llvm/llvm-project/pull/73497 rather than `main` as I write this). >From c415ffd79582e6a24e4da7152935c93cbe17210e Mon Sep 17 00:00:00 2001 From: Tim Northover <tnortho...@apple.com> Date: Wed, 22 Nov 2023 14:10:31 +0000 Subject: [PATCH] AArch64: add support for currently released Apple CPUs. These are still v8.6a so mostly just a copy/paste job. --- clang/test/Misc/target-invalid-cpu-note.c | 4 +-- .../llvm/TargetParser/AArch64TargetParser.h | 9 +++++++ llvm/lib/Target/AArch64/AArch64.td | 25 ++++++++++++++++++- llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 ++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 + .../TargetParser/TargetParserTest.cpp | 22 +++++++++++++++- 6 files changed, 59 insertions(+), 4 deletions(-) diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 693f47a78b7fa57..c7146e63add5f20 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 38ccca56336abb9..734bb2e3098310f 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -603,6 +603,10 @@ inline constexpr CpuInfo CpuInfos[] = { {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_BF16, AArch64::AEK_I8MM}))}, + {"apple-a17", ARMV8_6A, + (AArch64::ExtensionBitset( + {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP16, AArch64::AEK_FP16FML}))}, {"apple-m1", ARMV8_5A, (AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, @@ -612,6 +616,11 @@ inline constexpr CpuInfo CpuInfos[] = { {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_BF16, AArch64::AEK_I8MM}))}, + {"apple-m3", ARMV8_6A, + (AArch64::ExtensionBitset( + {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP16, AArch64::AEK_FP16FML}))}, + {"apple-s4", ARMV8_3A, (AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16}))}, diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 914ad0b68a624f6..ff256c9a8ccdf46 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -1147,6 +1147,22 @@ def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", FeatureZCRegMove, FeatureZCZeroing]>; +def TuneAppleA17 : SubtargetFeature<"apple-a17", "ARMProcFamily", "AppleA17", + "Apple A17", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureDisableLatencySchedHeuristic, + FeatureFuseAddress, + FeatureFuseAES, + FeatureFuseArithmeticLogic, + FeatureFuseCCSelect, + FeatureFuseCryptoEOR, + FeatureFuseLiterals, + FeatureStorePairSuppress, + FeatureZCRegMove, + FeatureZCZeroing]>; + def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", [FeatureExynosCheapAsMoveHandling, @@ -1446,6 +1462,10 @@ def ProcessorFeatures { FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, FeatureHCX]; + list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, + FeatureNEON, FeaturePerfMon, FeatureSHA3, + FeatureFullFP16, FeatureFP16FML, + FeatureHCX]; list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, FeaturePerfMon]; list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, @@ -1629,12 +1649,15 @@ def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, [TuneAppleA15]>; def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; - +def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, + [TuneAppleA17]>; // Mac CPUs def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, [TuneAppleA14]>; def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, [TuneAppleA15]>; +def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16, + [TuneAppleA16]>; // watch CPUs. def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index edd1072e1c8088c..cf57d950ae8d7f6 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -184,6 +184,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case AppleA14: case AppleA15: case AppleA16: + case AppleA17: CacheLineSize = 64; PrefetchDistance = 280; MinPrefetchStride = 2048; @@ -192,6 +193,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case AppleA14: case AppleA15: case AppleA16: + case AppleA17: MaxInterleaveFactor = 4; break; default: diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index ae2bea62056eb2b..5535fd44bf1590c 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -51,6 +51,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { AppleA14, AppleA15, AppleA16, + AppleA17, Carmel, CortexA35, CortexA53, diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 96dbae7ece2e290..db3420520351705 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1408,6 +1408,16 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM})), "8.5-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "apple-a17", "armv8.6-a", "crypto-neon-fp-armv8", + (AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM})), + "8.6-A"), ARMCPUTestParams<AArch64::ExtensionBitset>( "apple-m1", "armv8.5-a", "crypto-neon-fp-armv8", (AArch64::ExtensionBitset( @@ -1427,6 +1437,16 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM})), "8.5-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "apple-m3", "armv8.6-a", "crypto-neon-fp-armv8", + (AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM})), + "8.6-A"), ARMCPUTestParams<AArch64::ExtensionBitset>( "apple-s4", "armv8.3-a", "crypto-neon-fp-armv8", (AArch64::ExtensionBitset( @@ -1606,7 +1626,7 @@ INSTANTIATE_TEST_SUITE_P( "8.2-A"))); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 65; +static constexpr unsigned NumAArch64CPUArchs = 67; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; _______________________________________________ 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