================
@@ -0,0 +1,35 @@
+// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m85 -mfloat-abi=hard -O2
-save-temps=obj -S -o - %s | FileCheck %s
+// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m55 -mfloat-abi=hard -O2
-save-temps=obj -S -o - %s | FileCheck %s
+
+// The below tests are to make sure that assembly directives do not lose mve
feature so that reassembly works with
+// mve floating point instructions.
+// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m85 -mfloat-abi=hard -O2 -c
-mthumb -save-temps=obj %s
+// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m55 -mfloat-abi=hard -O2 -c
-mthumb -save-temps=obj %s
+
+// REQUIRES: arm-registered-target
+
+// CHECK: .fpu fpv5-d16
+// CHECK-NEXT .arch_extension mve.fp
+
+#define DUMMY_CONST_1 (0.0012345F)
+
+typedef struct
+{
+ float a;
+ float b;
+ float c;
+ float d;
+} dummy_t;
+
+// CHECK-LABEL: foo
+// CHECK: vsub.f32
+// CHECK: vfma.f32
----------------
davemgreen wrote:
This looks like it is trying to SLP vectorize to vector operations? These
instructions will match both `vsub.f32 s6, s2, s10` and `vsub.f32 q6, q2, q1`
operations though.
https://github.com/llvm/llvm-project/pull/71545
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