Author: mzuckerm
Date: Mon Oct 10 00:45:54 2016
New Revision: 283716
URL: http://llvm.org/viewvc/llvm-project?rev=283716&view=rev
Log:
[x86][inline-asm][clang] accept 'v' constraint
Commit in the name of: Coby Tayree
1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x'
constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch &
mode (32/64).
2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)
This patch applies the needed changes to clang
LLVM patch: https://reviews.llvm.org/D25005
Differential Revision: D25004
Added:
cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c (with props)
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=283716&r1=283715&r2=283716&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Mon Oct 10 00:45:54 2016
@@ -4005,6 +4005,7 @@ X86TargetInfo::validateAsmConstraint(con
case 'u': // Second from top of floating point stack.
case 'q': // Any register accessible as [r]l: a, b, c, and d.
case 'y': // Any MMX register.
+ case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
case 'x': // Any SSE register.
case 'Q': // Any register accessible as [r]h: a, b, c, and d.
case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
@@ -4045,6 +4046,7 @@ bool X86TargetInfo::validateOperandSize(
case 't':
case 'u':
return Size <= 128;
+ case 'v':
case 'x':
if (SSELevel >= AVX512F)
// 512-bit zmm registers can be used if target supports AVX512F.
Added: cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c?rev=283716&view=auto
==============================================================================
--- cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c (added)
+++ cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c Mon Oct 10 00:45:54
2016
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu
x86-64 -o - | FileCheck %s --check-prefix SSE
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu
skylake -D AVX -o - | FileCheck %s --check-prefixes AVX,SSE
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu
skylake-avx512 -D AVX512 -D AVX -o - | FileCheck %s --check-prefixes
AVX512,AVX,SSE
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu
knl -D AVX -D AVX512 -o - | FileCheck %s --check-prefixes AVX512,AVX,SSE
+
+typedef float __m128 __attribute__ ((vector_size (16)));
+typedef float __m256 __attribute__ ((vector_size (32)));
+typedef float __m512 __attribute__ ((vector_size (64)));
+
+// SSE: call <4 x float> asm "vmovhlps $1, $2, $0",
"=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %0, <4 x float> %1)
+__m128 testXMM(__m128 _xmm0, long _l) {
+ __asm__("vmovhlps %1, %2, %0" :"=v"(_xmm0) : "v"(_l), "v"(_xmm0));
+ return _xmm0;
+}
+
+// AVX: call <8 x float> asm "vmovsldup $1, $0",
"=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %0)
+__m256 testYMM(__m256 _ymm0) {
+#ifdef AVX
+ __asm__("vmovsldup %1, %0" :"=v"(_ymm0) : "v"(_ymm0));
+#endif
+ return _ymm0;
+}
+
+// AVX512: call <16 x float> asm "vpternlogd $$0, $1, $2, $0",
"=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %0, <16 x float> %1)
+__m512 testZMM(__m512 _zmm0, __m512 _zmm1) {
+#ifdef AVX512
+ __asm__("vpternlogd $0, %1, %2, %0" :"=v"(_zmm0) : "v"(_zmm1), "v"(_zmm0));
+#endif
+ return _zmm0;
+}
Propchange: cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c
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Propchange: cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c
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Propchange: cfe/trunk/test/CodeGen/x86-inline-asm-v-constraint.c
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