HaohaiWen wrote: > Yes, I understand that this transform is only a step towards handling the > full pattern. I'm asking for a complete, working example of the original > motivating case. The snippets posted in [#68502 > (comment)](https://github.com/llvm/llvm-project/pull/68502#discussion_r1351618002) > do not appear to be correct, or I failed to assemble them correctly. Please > provide complete src and tgt functions that verify with alive2.
Oh... sorry, I made a wrong IR example. The real case looks like this: https://alive2.llvm.org/ce/z/-DXnJc Both %x and %y are i16. The first or/fshl swaps half of of i32. The rest swaps byte, 4bit, 2bit. I extended the fshl transformation to apply for both symmetric and asymmetric combination. https://github.com/llvm/llvm-project/pull/68502 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
