https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/71953
Extend pfalse and ptrue builtins with svcount_t return types to be enabled for
sve2p1 and sme2
>From 79c05d1f8554d5a4469b9501b61b47863f086ffa Mon Sep 17 00:00:00 2001
From: Matt Devereau <matthew.dever...@arm.com>
Date: Fri, 10 Nov 2023 13:40:31 +0000
Subject: [PATCH] Add SME2 builtins for pfalse and ptrue
Extend pfalse and ptrue builtins with svcount_t return types
to be enabled for sve2p1 and sme2
---
clang/include/clang/Basic/arm_sve.td | 7 ++--
clang/lib/Sema/Sema.cpp | 3 +-
.../acle_sme2_ptrue_pfalse_attr.c | 34 +++++++++++++++++++
3 files changed, 41 insertions(+), 3 deletions(-)
create mode 100644
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 3d4c2129565903d..eccf87ac94abb3f 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1861,8 +1861,6 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl",
MergeNone, "aarch64_sv
let TargetGuard = "sve2p1" in {
def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone,
"aarch64_sve_fclamp", [], []>;
-def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
-def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone]>;
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
@@ -1981,6 +1979,11 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
+ def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone]>;
+}
+
////////////////////////////////////////////////////////////////////////////////
// SME2
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index d7d8d2eaa37e1d6..e4f6a291a869c27 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2084,7 +2084,8 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
llvm::StringMap<bool> CallerFeatureMap;
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
if (!Builtin::evaluateRequiredTargetFeatures(
- "sve", CallerFeatureMap))
+ "sve", CallerFeatureMap) && !Builtin::evaluateRequiredTargetFeatures(
+ "sme", CallerFeatureMap))
Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty;
}
};
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
new file mode 100644
index 000000000000000..90d9434d87cf4a0
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include <arm_sve.h>
+
+// CHECK-LABEL: @test_svptrue_c8_attr(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svptrue_c8_attrv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svptrue_c8_attr(void) __arm_streaming {
+ return svptrue_c8();
+}
+
+// CHECK-LABEL: @test_svptrue_c(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z14test_svptrue_cv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svptrue_c(void) __arm_streaming {
+ return svpfalse_c();
+}
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