================
@@ -1457,6 +1457,24 @@ class AdvSIMD_GatherLoad_VS_Intrinsic
],
[IntrReadMem]>;
+class AdvSIMD_GatherLoadQ_VS_Intrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [
+ llvm_nxv1i1_ty,
+ llvm_anyvector_ty,
----------------
CarolineConcatto wrote:
So, why do we have the predicated vector as llvm_nxv1i1_ty? I was exception
something like
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, because I don't see any cast for
the predicate under EmitSVEGatherLoad. This line
Ops[0] = EmitSVEPredicateCast(
Ops[0], cast<llvm::ScalableVectorType>(F->getArg(0)->getType()));
would map to whatever is the type in the position 0.
Second, does it works if we replace the second llvm_anyvector_ty by
llvm_nxv2i64_ty? I do think the vector will always be 64 bits
https://github.com/llvm/llvm-project/pull/71290
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