================
@@ -1744,45 +1744,60 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
- // If the vector select parameter is an immediate in the range 0-15 then we
- // can emit it directly into the instruction as it's a legal operand.
- // Otherwise we must emit 0 as the vector select operand and modify the base
- // register instead.
+ // If the vector number is an immediate between 0 and 15 inclusive then we
can
+ // put that directly into the immediate field of the instruction. If it's
+ // outside of that range then we modify the base and slice by the greatest
+ // multiple of 15 smaller than that number and put the remainder in the
+ // instruction field. If it's not an immediate then we modify the base and
+ // slice registers by that number and put 0 in the instruction.
SDLoc DL(N);
- SDValue VecNum = N->getOperand(4), Base = N->getOperand(3),
- TileSlice = N->getOperand(2);
- int Imm = -1;
- if (auto ImmNode = dyn_cast<ConstantSDNode>(VecNum))
- Imm = ImmNode->getZExtValue();
+ SDValue TileSlice = N->getOperand(2);
+ SDValue Base = N->getOperand(3);
+ SDValue VecNum = N->getOperand(4);
+ SDValue Remainder = CurDAG->getTargetConstant(0, DL, MVT::i32);
+
+ // true if the base and slice registers need to me modified
----------------
sdesmalen-arm wrote:
```suggestion
// true if the base and slice registers need to be modified
```
https://github.com/llvm/llvm-project/pull/68565
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