https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source high-performance RISC-V processor. According to the official [documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/), NanHu core supports `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`. I found that NanHu also supports `zicbom` and `zicboz`. You can find them in the [source code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436). Features supported by NanHu have been confirmed by @poemonsense. See also #70232. >From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001 From: Yingwei Zheng <dtcxzyw2...@gmail.com> Date: Thu, 26 Oct 2023 13:47:39 +0800 Subject: [PATCH] [RISCV] Add processor definition for XiangShan-NanHu Co-authored-by: SForeKeeper <zkl...@gmail.com> --- clang/test/Driver/riscv-cpus.c | 14 ++++++++++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- llvm/lib/Target/RISCV/RISCVProcessors.td | 21 +++++++++++++++++++++ 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 3eaceedce685fc6..70f0a63336bd478 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -20,6 +20,17 @@ // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s +// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval" +// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d" + // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s @@ -62,6 +73,9 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s +// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" + // Check mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s // MTUNE-GENERIC-32: "-tune-cpu" "generic" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index b2a04ebdbce628f..8e91eb4c62dd259 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index e4008d145ffa572..427e15bea2f8dce 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -243,3 +243,24 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", FeatureStdExtZicbop, FeatureStdExtZicboz, FeatureVendorXVentanaCondOps]>; + +def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", + NoSchedModel, + [Feature64Bit, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZkn, + FeatureStdExtZksed, + FeatureStdExtZksh, + FeatureStdExtSvinval, + FeatureStdExtZicbom, + FeatureStdExtZicboz]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
