================
@@ -11595,6 +11595,50 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op,
SelectionDAG &DAG) const {
llvm_unreachable("ERROR:Should return for all cases within swtich.");
}
+// Lower mffsl intrinsic with mffs in targets without ISA 3.0
+static SDValue lowerMFFSL(SDValue Op, SelectionDAG &DAG,
----------------
nemanjai wrote:
I wonder if we actually need this. The reason `mffsl` exists is because it is a
lightweight version of `mffs`. In order to make it lightweight, the instruction
only extracts some bits from the FPSCR.
So in order to match the semantics, we end up doing the heavy weight
instruction, materializing a 64-bit constant, moving to a GPR, masking out the
bits and then moving it back to an FPR. So a user's attempt to use the
lightweight version ends up costing them more than the heavy weight version on
older CPU's.
Can we not just reject it on older CPU's and force the user to use the heavy
weight instruction?
https://github.com/llvm/llvm-project/pull/67299
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