https://github.com/dfszabo updated
https://github.com/llvm/llvm-project/pull/65465
From ea6ac8788b383ba22073e631d12a80f421c36a1a Mon Sep 17 00:00:00 2001
From: dszabo <szabodavidfer...@gmail.com>
Date: Mon, 18 Sep 2023 17:47:15 +0200
Subject: [PATCH] [CodeGen] Allow mixed scalar type constraints for inline asm
---
.../SelectionDAG/SelectionDAGBuilder.cpp | 7 ++--
.../CodeGen/SelectionDAG/TargetLowering.cpp | 7 ++--
llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll | 32 +++++++++++++++++++
3 files changed, 42 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 7a85f19f3df5d3e..10e55e0cfe2ef5d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8841,8 +8841,11 @@ static void patchMatchingInput(const
SDISelAsmOperandInfo &OpInfo,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
MatchingOpInfo.ConstraintVT);
- if ((OpInfo.ConstraintVT.isInteger() !=
- MatchingOpInfo.ConstraintVT.isInteger()) ||
+ const bool OutOpIsIntOrFP =
+ OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.isFloatingPoint();
+ const bool InOpInfoIsIntOrFP = MatchingOpInfo.ConstraintVT.isInteger() ||
+ MatchingOpInfo.ConstraintVT.isFloatingPoint();
+ if ((OutOpIsIntOrFP != InOpInfoIsIntOrFP) ||
(MatchRC.second != InputRC.second)) {
// FIXME: error out in a more elegant fashion
report_fatal_error("Unsupported asm: input constraint"
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 23c1486f711d727..89d7bbd41f0be8f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5687,8 +5687,11 @@ TargetLowering::ParseConstraints(const DataLayout &DL,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
Input.ConstraintVT);
- if ((OpInfo.ConstraintVT.isInteger() !=
- Input.ConstraintVT.isInteger()) ||
+ const bool OutOpIsIntOrFP = OpInfo.ConstraintVT.isInteger() ||
+ OpInfo.ConstraintVT.isFloatingPoint();
+ const bool InOpIsIntOrFP = Input.ConstraintVT.isInteger() ||
+ Input.ConstraintVT.isFloatingPoint();
+ if ((OutOpIsIntOrFP != InOpIsIntOrFP) ||
(MatchRC.second != InputRC.second)) {
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
diff --git a/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
b/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
new file mode 100644
index 000000000000000..9470553b2fbc43d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; C source used for generating this test:
+
+; unsigned test(float f)
+; {
+; unsigned i;
+; asm volatile ("" : "=r" (i) : "0" (f));
+; return i;
+; }
+
+
+define i32 @test(float %f) {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movss %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: retq
+entry:
+ %f.addr = alloca float, align 4
+ %i = alloca i32, align 4
+ store float %f, ptr %f.addr, align 4
+ %0 = load float, ptr %f.addr, align 4
+ %1 = call i32 asm sideeffect "", "=r,0,~{dirflag},~{fpsr},~{flags}"(float %0)
+ store i32 %1, ptr %i, align 4
+ %2 = load i32, ptr %i, align 4
+ ret i32 %2
+}
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