https://github.com/bwendling updated
https://github.com/llvm/llvm-project/pull/67193
>From 6db37f7f76347a7821d9a95c0fdac4e250df2e78 Mon Sep 17 00:00:00 2001
From: Bill Wendling <mo...@google.com>
Date: Fri, 22 Sep 2023 12:35:09 -0700
Subject: [PATCH 1/2] [CodeGen] Avoid potential sideeffects from XOR
XOR may change flag values (e.g. for X86 gprs). In the case where that's
not desirable, specify that buildClearRegister() should use MOV instead.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 7 +++--
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 14 +++++----
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 4 +--
llvm/lib/Target/X86/X86InstrInfo.cpp | 31 +++++++++++++-------
llvm/lib/Target/X86/X86InstrInfo.h | 4 +--
5 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 04859a50d6fdeb4..7c2bd83d1d623ef 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2057,10 +2057,13 @@ class TargetInstrInfo : public MCInstrInfo {
"Target didn't implement TargetInstrInfo::insertOutlinedCall!");
}
- /// Insert an architecture-specific instruction to clear a register.
+ /// Insert an architecture-specific instruction to clear a register. If you
+ /// need to avoid sideeffects (e.g. XOR on x86), set \p NoSideEffects to \p
+ /// true.
virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator Iter,
- DebugLoc &DL) const {
+ DebugLoc &DL,
+ bool NoSideEffects = false) const {
llvm_unreachable(
"Target didn't implement TargetInstrInfo::buildClearRegister!");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a1e6a8177c10013..3b1e301e576a1b1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -8337,21 +8337,23 @@ bool
AArch64InstrInfo::shouldOutlineFromFunctionByDefault(
void AArch64InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator Iter,
- DebugLoc &DL) const {
+ DebugLoc &DL,
+ bool NoSideEffects) const {
const MachineFunction &MF = *MBB.getParent();
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo &TRI = *STI.getRegisterInfo();
if (TRI.isGeneralPurposeRegister(MF, Reg)) {
- BuildMI(MBB, Iter, DL, get(AArch64::MOVi64imm), Reg)
- .addImm(0);
+ BuildMI(MBB, Iter, DL, get(AArch64::MOVZXi), Reg)
+ .addImm(0)
+ .addImm(0);
} else if (STI.hasSVE()) {
BuildMI(MBB, Iter, DL, get(AArch64::DUP_ZI_D), Reg)
- .addImm(0)
- .addImm(0);
+ .addImm(0)
+ .addImm(0);
} else {
BuildMI(MBB, Iter, DL, get(AArch64::MOVIv2d_ns), Reg)
- .addImm(0);
+ .addImm(0);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 4a4d87c1b1f6ba5..5c5e7e4fe39068a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -320,8 +320,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator Iter,
- DebugLoc &DL) const override;
+ MachineBasicBlock::iterator Iter, DebugLoc &DL,
+ bool NoSideEffects = false) const override;
/// Returns the vector element size (B, H, S or D) of an SVE opcode.
uint64_t getElementSizeForOpcode(unsigned Opc) const;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp
b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 73675a868239ea1..24a7d632f951385 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -9796,27 +9796,34 @@ X86InstrInfo::insertOutlinedCall(Module &M,
MachineBasicBlock &MBB,
return It;
}
-void X86InstrInfo::buildClearRegister(Register Reg,
- MachineBasicBlock &MBB,
+void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator Iter,
- DebugLoc &DL) const {
+ DebugLoc &DL, bool NoSideEffects) const {
const MachineFunction &MF = *MBB.getParent();
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
const TargetRegisterInfo &TRI = getRegisterInfo();
if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
- // FIXME: Ignore MMX registers?
+ // FIXME: Should we ignore MMX registers?
return;
if (TRI.isGeneralPurposeRegister(MF, Reg)) {
- BuildMI(MBB, Iter, DL, get(X86::XOR32rr), Reg)
- .addReg(Reg, RegState::Undef)
- .addReg(Reg, RegState::Undef);
+ // Convert register to the 32-bit version.
+ Reg = getX86SubSuperRegister(Reg, 32);
+
+ if (NoSideEffects)
+ // XOR affects flags, so use a MOV instead.
+ BuildMI(MBB, Iter, DL, get(X86::MOV32ri), Reg).addImm(0);
+ else
+ BuildMI(MBB, Iter, DL, get(X86::XOR32rr), Reg)
+ .addReg(Reg, RegState::Undef)
+ .addReg(Reg, RegState::Undef);
} else if (X86::VR128RegClass.contains(Reg)) {
// XMM#
if (!ST.hasSSE1())
return;
+ // PXOR is safe to use because it doesn't affect flags.
BuildMI(MBB, Iter, DL, get(X86::PXORrr), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
@@ -9825,6 +9832,7 @@ void X86InstrInfo::buildClearRegister(Register Reg,
if (!ST.hasAVX())
return;
+ // VPXOR is safe to use because it doesn't affect flags.
BuildMI(MBB, Iter, DL, get(X86::VPXORrr), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
@@ -9833,6 +9841,7 @@ void X86InstrInfo::buildClearRegister(Register Reg,
if (!ST.hasAVX512())
return;
+ // VPXORY is safe to use because it doesn't affect flags.
BuildMI(MBB, Iter, DL, get(X86::VPXORYrr), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
@@ -9844,9 +9853,11 @@ void X86InstrInfo::buildClearRegister(Register Reg,
if (!ST.hasVLX())
return;
- BuildMI(MBB, Iter, DL, get(ST.hasBWI() ? X86::KXORQrr : X86::KXORWrr), Reg)
- .addReg(Reg, RegState::Undef)
- .addReg(Reg, RegState::Undef);
+ // KXOR is safe to use because it doesn't affect flags.
+ unsigned Op = ST.hasBWI() ? X86::KXORQrr : X86::KXORWrr;
+ BuildMI(MBB, Iter, DL, get(Op), Reg)
+ .addReg(Reg, RegState::Undef)
+ .addReg(Reg, RegState::Undef);
}
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h
b/llvm/lib/Target/X86/X86InstrInfo.h
index 8119302f73e8b36..a5ad618ef4b6415 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -574,8 +574,8 @@ class X86InstrInfo final : public X86GenInstrInfo {
outliner::Candidate &C) const override;
void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator Iter,
- DebugLoc &DL) const override;
+ MachineBasicBlock::iterator Iter, DebugLoc &DL,
+ bool NoSideEffects = false) const override;
bool verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const override;
>From 3fd234487dd5796043a4f5df4cf662f2c0373bf0 Mon Sep 17 00:00:00 2001
From: Bill Wendling <mo...@google.com>
Date: Fri, 22 Sep 2023 14:12:43 -0700
Subject: [PATCH 2/2] Fix formatting.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3b1e301e576a1b1..ddd496d127732b5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -8344,16 +8344,11 @@ void AArch64InstrInfo::buildClearRegister(Register Reg,
MachineBasicBlock &MBB,
const AArch64RegisterInfo &TRI = *STI.getRegisterInfo();
if (TRI.isGeneralPurposeRegister(MF, Reg)) {
- BuildMI(MBB, Iter, DL, get(AArch64::MOVZXi), Reg)
- .addImm(0)
- .addImm(0);
+ BuildMI(MBB, Iter, DL, get(AArch64::MOVZXi), Reg).addImm(0).addImm(0);
} else if (STI.hasSVE()) {
- BuildMI(MBB, Iter, DL, get(AArch64::DUP_ZI_D), Reg)
- .addImm(0)
- .addImm(0);
+ BuildMI(MBB, Iter, DL, get(AArch64::DUP_ZI_D), Reg).addImm(0).addImm(0);
} else {
- BuildMI(MBB, Iter, DL, get(AArch64::MOVIv2d_ns), Reg)
- .addImm(0);
+ BuildMI(MBB, Iter, DL, get(AArch64::MOVIv2d_ns), Reg).addImm(0);
}
}
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