https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/66860
None
>From 041da389550eeb7865a91b8b0e723a04ed2f84e1 Mon Sep 17 00:00:00 2001
From: 4vtomat <brandon...@sifive.com>
Date: Tue, 19 Sep 2023 23:06:01 -0700
Subject: [PATCH] [RISCV] Fix wrong implication for zvknhb.
---
clang/include/clang/Basic/riscv_vector.td | 9 ++++++++-
.../include/clang/Support/RISCVVIntrinsicUtils.h | 5 +++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 1 +
clang/test/Sema/zvk-invalid-zvknha.c | 11 +++++++++++
clang/utils/TableGen/RISCVVEmitter.cpp | 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 --
llvm/lib/Target/RISCV/RISCVFeatures.td | 16 +++++++++++-----
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 16 +++++++++++-----
llvm/test/CodeGen/RISCV/attributes.ll | 16 ++++++++--------
llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll | 6 ++++++
llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll | 6 ++++++
llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll | 6 ++++++
llvm/test/MC/RISCV/attribute-arch.s | 8 ++++----
llvm/test/MC/RISCV/rvv/zvknh.s | 6 +++---
14 files changed, 79 insertions(+), 30 deletions(-)
create mode 100644 clang/test/Sema/zvk-invalid-zvknha.c
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 60a1a2b2be6fb40..8d9c4237e59bf9f 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2997,8 +2997,15 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked =
false in {
defm vaesz : RVVOutBuiltinSetZvk<HasVV=0>;
}
- // zvknha or zvknhb
+ // zvknha
let RequiredFeatures = ["Zvknha"] in {
+ defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"i">;
+ defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"i">;
+ defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"i">;
+ }
+
+ // zvknhb
+ let RequiredFeatures = ["Zvknhb"] in {
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 8ba57d77221dc52..b703259a777ec85 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -491,8 +491,9 @@ enum RVVRequire : uint16_t {
RVV_REQ_Zvkg = 1 << 6,
RVV_REQ_Zvkned = 1 << 7,
RVV_REQ_Zvknha = 1 << 8,
- RVV_REQ_Zvksed = 1 << 9,
- RVV_REQ_Zvksh = 1 << 10,
+ RVV_REQ_Zvknhb = 1 << 9,
+ RVV_REQ_Zvksed = 1 << 10,
+ RVV_REQ_Zvksh = 1 << 11,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
};
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index ae584dc68719901..cf5c074761e017e 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -211,6 +211,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"experimental-zvkg", RVV_REQ_Zvkg},
{"experimental-zvkned", RVV_REQ_Zvkned},
{"experimental-zvknha", RVV_REQ_Zvknha},
+ {"experimental-zvknhb", RVV_REQ_Zvknhb},
{"experimental-zvksed", RVV_REQ_Zvksed},
{"experimental-zvksh", RVV_REQ_Zvksh}};
diff --git a/clang/test/Sema/zvk-invalid-zvknha.c
b/clang/test/Sema/zvk-invalid-zvknha.c
new file mode 100644
index 000000000000000..0ce2e321a175f5f
--- /dev/null
+++ b/clang/test/Sema/zvk-invalid-zvknha.c
@@ -0,0 +1,11 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature
+experimental-zvknha %s -fsyntax-only -verify
+
+#include <riscv_vector.h>
+
+void test_zvk_features() {
+ // zvknhb
+ __riscv_vsha2ch_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2ch_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+ __riscv_vsha2cl_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2cl_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+ __riscv_vsha2ms_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2ms_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+}
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 41025926058ed07..368136208d9a751 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -662,6 +662,7 @@ void RVVEmitter::createRVVIntrinsics(
.Case("Zvkg", RVV_REQ_Zvkg)
.Case("Zvkned", RVV_REQ_Zvkned)
.Case("Zvknha", RVV_REQ_Zvknha)
+ .Case("Zvknhb", RVV_REQ_Zvknhb)
.Case("Zvksed", RVV_REQ_Zvksed)
.Case("Zvksh", RVV_REQ_Zvksh)
.Default(RVV_REQ_None);
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a3045657e63b724..8f9ba2672e75c6e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1013,7 +1013,6 @@ static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
-static const char *ImpliedExtsZvknhb[] = {"zvknha"};
static const char *ImpliedExtsZvks[] = {"zvkb", "zvksed", "zvksh", "zvkt"};
static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
@@ -1080,7 +1079,6 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"zvkn"}, {ImpliedExtsZvkn}},
{{"zvknc"}, {ImpliedExtsZvknc}},
{{"zvkng"}, {ImpliedExtsZvkng}},
- {{"zvknhb"}, {ImpliedExtsZvknhb}},
{{"zvks"}, {ImpliedExtsZvks}},
{{"zvksc"}, {ImpliedExtsZvksc}},
{{"zvksg"}, {ImpliedExtsZvksg}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 5231f3c3cf3df2d..711156372550572 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -599,15 +599,21 @@ def HasStdExtZvkned :
Predicate<"Subtarget->hasStdExtZvkned()">,
def FeatureStdExtZvknha
: SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
-
-def FeatureStdExtZvknhb
- : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
- "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
- [FeatureStdExtZvknha]>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of
FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
+def FeatureStdExtZvknhb
+ : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+ "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
+def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
+ AssemblerPredicate<(all_of
FeatureStdExtZvknhb),
+ "'Zvknhb' (Vector SHA-2 (SHA-256 and
SHA-512))">;
+
+def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() ||
Subtarget->hasStdExtZvknhb()">,
+ AssemblerPredicate<(any_of
FeatureStdExtZvknha, FeatureStdExtZvknhb),
+ "'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
+
def FeatureStdExtZvksed
: SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
"'Zvksed' (SM4 Block Cipher Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 062529c054ecd46..04a45eeb8ba4dc3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -136,11 +136,11 @@ let Predicates = [HasStdExtZvkg], RVVConstraint =
NoConstraint in {
def VGMUL_VV : PALUVs2NoVm<0b101000, 0b10001, OPMVV, "vgmul.vv">;
} // Predicates = [HasStdExtZvkg]
-let Predicates = [HasStdExtZvknha], RVVConstraint = NoConstraint in {
+let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = NoConstraint in {
def VSHA2CH_VV : PALUVVNoVm<0b101110, OPMVV, "vsha2ch.vv">;
def VSHA2CL_VV : PALUVVNoVm<0b101111, OPMVV, "vsha2cl.vv">;
def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">;
-} // Predicates = [HasStdExtZvknha]
+} // Predicates = [HasStdExtZvknhaOrZvknhb]
let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
@@ -390,11 +390,11 @@ let Predicates = [HasStdExtZvkned] in {
defm PseudoVAESZ : VPseudoVALU_S_NoMask_Zvk;
} // Predicates = [HasStdExtZvkned]
-let Predicates = [HasStdExtZvknha] in {
+let Predicates = [HasStdExtZvknhaOrZvknhb] in {
defm PseudoVSHA2CH : VPseudoVALU_VV_NoMask_Zvk;
defm PseudoVSHA2CL : VPseudoVALU_VV_NoMask_Zvk;
defm PseudoVSHA2MS : VPseudoVALU_VV_NoMask_Zvk;
-} // Predicates = [HasStdExtZvknha]
+} // Predicates = [HasStdExtZvknhaOrZvknhb]
let Predicates = [HasStdExtZvksed] in {
defm PseudoVSM4K : VPseudoVALU_VI_NoMaskTU_Zvk;
@@ -874,10 +874,16 @@ let Predicates = [HasStdExtZvkned] in {
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvknha] in {
+ defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH",
I32IntegerVectors>;
+ defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH",
I32IntegerVectors>;
+ defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS",
I32IntegerVectors>;
+} // Predicates = [HasStdExtZvknha]
+
+let Predicates = [HasStdExtZvknhb] in {
defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH",
I32I64IntegerVectors>;
defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH",
I32I64IntegerVectors>;
defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS",
I32I64IntegerVectors>;
-} // Predicates = [HasStdExtZvknha]
+} // Predicates = [HasStdExtZvknhb]
let Predicates = [HasStdExtZvksed] in {
defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vsm4k", "PseudoVSM4K",
I32IntegerVectors>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 29eaaee57868a83..f6d4305de56c03d 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -248,12 +248,12 @@
; RV32ZVBC: .attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
-; RV32ZVKN: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNC: .attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKN: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNC: .attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
-; RV32ZVKNG: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNG: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
-; RV32ZVKNHB: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHB: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKS: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSC: .attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
@@ -337,12 +337,12 @@
; RV64ZVBC: .attribute 5,
"rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
-; RV64ZVKN: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNC: .attribute 5,
"rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKN: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNC: .attribute 5,
"rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
-; RV64ZVKNG: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNG: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
-; RV64ZVKNHB: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHB: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKS: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
; RV64ZVKSC: .attribute 5,
"rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
index 52c43f9713a6080..7ee3ffb19c71f6f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
@@ -3,6 +3,12 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+v,+experimental-zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+
+; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
index 49ae2858e1461ba..9de122189f42674 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
@@ -3,6 +3,12 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+v,+experimental-zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+
+; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
index d26c9f5a373862f..ee458daa5fc4875 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
@@ -3,6 +3,12 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+v,+experimental-zvknha,+experimental-zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64
-mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
+
+; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index bf40eda456edf13..7da513cf1c3328d 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -124,19 +124,19 @@
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvkn1p0"
-# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvknc1p0"
-# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvkng1p0"
-# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvknha1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvknhb1p0"
-# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvkned1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s
index a00fdcc50ea74e4..9d833a14e419f6e 100644
--- a/llvm/test/MC/RISCV/rvv/zvknh.s
+++ b/llvm/test/MC/RISCV/rvv/zvknh.s
@@ -19,16 +19,16 @@ vsha2ms.vv v10, v9, v8
# CHECK-INST: vsha2ms.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x25,0x94,0xb6]
# CHECK-UNKNOWN: 77 25 94 b6 <unknown>
-# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2
(SHA-256 only)){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb'
(Vector SHA-2){{$}}
vsha2ch.vv v10, v9, v8
# CHECK-INST: vsha2ch.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x25,0x94,0xba]
# CHECK-UNKNOWN: 77 25 94 ba <unknown>
-# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2
(SHA-256 only)){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb'
(Vector SHA-2){{$}}
vsha2cl.vv v10, v9, v8
# CHECK-INST: vsha2cl.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x25,0x94,0xbe]
# CHECK-UNKNOWN: 77 25 94 be <unknown>
-# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2
(SHA-256 only)){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb'
(Vector SHA-2){{$}}
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