https://github.com/mgudim updated
https://github.com/llvm/llvm-project/pull/65535
>From 8dff19fbb00ce7dcd818eb851601b36a7cdeea42 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgu...@gmail.com>
Date: Wed, 6 Sep 2023 17:15:56 -0400
Subject: [PATCH 1/2] [RISCV] Added definition of Ventana veyron-v1 processor.
---
clang/test/Driver/riscv-cpus.c | 25 +++++++++++++++++++++++
clang/test/Misc/target-invalid-cpu-note.c | 2 +-
llvm/lib/Target/RISCV/RISCVProcessors.td | 22 ++++++++++++++++++++
3 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bd8488d81c0b156..3eaceedce685fc6 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -37,6 +37,31 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max |
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck
-check-prefix=MCPU-VEYRON-V1 %s
+// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
+// MCPU-VEYRON-V1: "-target-feature" "+m"
+// MCPU-VEYRON-V1: "-target-feature" "+a"
+// MCPU-VEYRON-V1: "-target-feature" "+f"
+// MCPU-VEYRON-V1: "-target-feature" "+d"
+// MCPU-VEYRON-V1: "-target-feature" "+c"
+// MCPU-VEYRON-V1: "-target-feature" "+zicbom"
+// MCPU-VEYRON-V1: "-target-feature" "+zicbop"
+// MCPU-VEYRON-V1: "-target-feature" "+zicboz"
+// MCPU-VEYRON-V1: "-target-feature" "+zicntr"
+// MCPU-VEYRON-V1: "-target-feature" "+zicsr"
+// MCPU-VEYRON-V1: "-target-feature" "+zifencei"
+// MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
+// MCPU-VEYRON-V1: "-target-feature" "+zihpm"
+// MCPU-VEYRON-V1: "-target-feature" "+zba"
+// MCPU-VEYRON-V1: "-target-feature" "+zbb"
+// MCPU-VEYRON-V1: "-target-feature" "+zbc"
+// MCPU-VEYRON-V1: "-target-feature" "+zbs"
+// MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
+// MCPU-VEYRON-V1: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck
-check-prefix=MTUNE-VEYRON-V1 %s
+// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck
-check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index c44bd6087af4132..871ac090fedba27 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, generic, rocket, sifive-7-series, veyron-v1{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 01291001cd7ca24..402ec20fe39ab1c 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -201,3 +201,25 @@ def SYNTACORE_SCR1_MAX :
RISCVProcessorModel<"syntacore-scr1-max",
FeatureStdExtM,
FeatureStdExtC],
[TuneNoDefaultUnroll]>;
+
+def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZihintpause,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureVendorXVentanaCondOps]>;
>From 5fe9e82d849b85022a0a95016c65066dbae27e4d Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgu...@gmail.com>
Date: Mon, 18 Sep 2023 14:40:47 -0400
Subject: [PATCH 2/2] Fixed failing test.
---
clang/test/Misc/target-invalid-cpu-note.c | 4 +--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 34 +++----------------
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 16 ++++-----
3 files changed, 15 insertions(+), 39 deletions(-)
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 871ac090fedba27..a639b0ddde85e5a 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, generic, rocket, sifive-7-series, veyron-v1{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e74d184c0a35d04..b73b46754d06d50 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11633,39 +11633,15 @@ static SDValue performXORCombine(SDNode *N,
SelectionDAG &DAG,
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
}
-/// According to the property that indexed load/store instructions zero-extend
-/// their indices, try to narrow the type of index operand.
+// According to the property that indexed load/store instructions
+// zero-extended their indices, \p narrowIndex tries to narrow the type of
index
+// operand if it is matched to pattern (shl (zext x to ty), C) and bits(x) + C
<
+// bits(ty).
static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG
&DAG) {
if (isIndexTypeSigned(IndexType))
return false;
- if (!N->hasOneUse())
- return false;
-
- EVT VT = N.getValueType();
- SDLoc DL(N);
-
- // In general, what we're doing here is seeing if we can sink a truncate to
- // a smaller element type into the expression tree building our index.
- // TODO: We can generalize this and handle a bunch more cases if useful.
-
- // Narrow a buildvector to the narrowest element type. This requires less
- // work and less register pressure at high LMUL, and creates smaller
constants
- // which may be cheaper to materialize.
- if (ISD::isBuildVectorOfConstantSDNodes(N.getNode())) {
- KnownBits Known = DAG.computeKnownBits(N);
- unsigned ActiveBits = std::max(8u, Known.countMaxActiveBits());
- LLVMContext &C = *DAG.getContext();
- EVT ResultVT = EVT::getIntegerVT(C, ActiveBits).getRoundIntegerType(C);
- if (ResultVT.bitsLT(VT.getVectorElementType())) {
- N = DAG.getNode(ISD::TRUNCATE, DL,
- VT.changeVectorElementType(ResultVT), N);
- return true;
- }
- }
-
- // Handle the pattern (shl (zext x to ty), C) and bits(x) + C < bits(ty).
- if (N.getOpcode() != ISD::SHL)
+ if (N.getOpcode() != ISD::SHL || !N->hasOneUse())
return false;
SDValue N0 = N.getOperand(0);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index ac5c11ca88df51a..3711f014e06478b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -13027,8 +13027,8 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) {
; RV32-NEXT: lui a1, %hi(.LCPI107_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI107_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle8.v v9, (a1)
-; RV32-NEXT: vluxei8.v v8, (a0), v9
+; RV32-NEXT: vle32.v v10, (a1)
+; RV32-NEXT: vluxei32.v v8, (a0), v10
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_strided_2xSEW:
@@ -13036,8 +13036,8 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) {
; RV64V-NEXT: lui a1, %hi(.LCPI107_0)
; RV64V-NEXT: addi a1, a1, %lo(.LCPI107_0)
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64V-NEXT: vle8.v v9, (a1)
-; RV64V-NEXT: vluxei8.v v8, (a0), v9
+; RV64V-NEXT: vle64.v v12, (a1)
+; RV64V-NEXT: vluxei64.v v8, (a0), v12
; RV64V-NEXT: ret
;
; RV64ZVE32F-LABEL: mgather_strided_2xSEW:
@@ -13144,8 +13144,8 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) {
; RV32-NEXT: lui a1, %hi(.LCPI108_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI108_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle8.v v9, (a1)
-; RV32-NEXT: vluxei8.v v8, (a0), v9
+; RV32-NEXT: vle32.v v10, (a1)
+; RV32-NEXT: vluxei32.v v8, (a0), v10
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_gather_2xSEW:
@@ -13153,8 +13153,8 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) {
; RV64V-NEXT: lui a1, %hi(.LCPI108_0)
; RV64V-NEXT: addi a1, a1, %lo(.LCPI108_0)
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64V-NEXT: vle8.v v9, (a1)
-; RV64V-NEXT: vluxei8.v v8, (a0), v9
+; RV64V-NEXT: vle64.v v12, (a1)
+; RV64V-NEXT: vluxei64.v v8, (a0), v12
; RV64V-NEXT: ret
;
; RV64ZVE32F-LABEL: mgather_gather_2xSEW:
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