================ @@ -1599,6 +1600,15 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, State.Column += Current.ColumnWidth; State.NextToken = State.NextToken->Next; + // Verilog case labels are are on the same unwrapped lines as the statements + // that follow. TokenAnnotator identifies them and sets MustBreakBefore. + // Indentation is taken care of here. A case label can only have 1 statement ---------------- owenca wrote:
Typo: `are are`. Also, use single space after `.`. https://github.com/llvm/llvm-project/pull/65861 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
