dpaoliello added inline comments.
================ Comment at: llvm/lib/Target/AArch64/AArch64CallingConvention.td:555-557 +def CSR_Win_AArch64_Arm64EC_Thunk : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, + X25, X26, X27, X28, FP, LR, + (sequence "Q%u", 6, 15))>; ---------------- I've been hitting asserts in `computeCalleeSaveRegisterPairs` due to this: LLVM doesn't support gaps when saving registers for Windows (~line 2744 of AArch64FrameLowering.cpp), so placing the smaller registers before the larger ones causes issues if those smaller ones aren't paired (the `assert(OffsetPre % Scale == 0);` fires since `OffsetPre` will be a multiple of 8 but `Scale` will be 16). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157547/new/ https://reviews.llvm.org/D157547 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
