This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG29f11e4fb704: [RISCV] Bump vector crypto to v1.0 RC2
(authored by 4vtomat).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158067/new/
https://reviews.llvm.org/D158067
Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
llvm/docs/RISCVUsage.rst
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/rvv/vandn.ll
llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
llvm/test/CodeGen/RISCV/rvv/vrev8.ll
llvm/test/CodeGen/RISCV/rvv/vrol.ll
llvm/test/CodeGen/RISCV/rvv/vror.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rvv/zvbb.s
llvm/test/MC/RISCV/rvv/zvkb.s
Index: llvm/test/MC/RISCV/rvv/zvkb.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkb.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 04 <unknown>
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 04 <unknown>
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 94 48 <unknown>
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 a5 94 48 <unknown>
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 54 <unknown>
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 54 <unknown>
+
+vror.vv v10, v9, v8, v0.t
+# CHECK-INST: vror.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 50 <unknown>
+
+vror.vx v10, v9, a0, v0.t
+# CHECK-INST: vror.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 50 <unknown>
+
+vror.vi v10, v9, 33, v0.t
+# CHECK-INST: vror.vi v10, v9, 33, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 b5 90 54 <unknown>
Index: llvm/test/MC/RISCV/rvv/zvbb.s
===================================================================
--- llvm/test/MC/RISCV/rvv/zvbb.s
+++ llvm/test/MC/RISCV/rvv/zvbb.s
@@ -8,98 +8,44 @@
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vandn.vv v10, v9, v8, v0.t
-# CHECK-INST: vandn.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 05 94 04 <unknown>
-
-vandn.vx v10, v9, a0, v0.t
-# CHECK-INST: vandn.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 45 95 04 <unknown>
-
-vbrev8.v v10, v9, v0.t
-# CHECK-INST: vbrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 25 94 48 <unknown>
-
vbrev.v v10, v9, v0.t
# CHECK-INST: vbrev.v v10, v9, v0.t
# CHECK-ENCODING: [0x57,0x25,0x95,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 25 95 48 <unknown>
vclz.v v10, v9, v0.t
# CHECK-INST: vclz.v v10, v9, v0.t
# CHECK-ENCODING: [0x57,0x25,0x96,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 25 96 48 <unknown>
vcpop.v v10, v9, v0.t
# CHECK-INST: vcpop.v v10, v9, v0.t
# CHECK-ENCODING: [0x57,0x25,0x97,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 25 97 48 <unknown>
vctz.v v10, v9, v0.t
# CHECK-INST: vctz.v v10, v9, v0.t
# CHECK-ENCODING: [0x57,0xa5,0x96,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 a5 96 48 <unknown>
-vrev8.v v10, v9, v0.t
-# CHECK-INST: vrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 a5 94 48 <unknown>
-
-vrol.vv v10, v9, v8, v0.t
-# CHECK-INST: vrol.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 05 94 54 <unknown>
-
-vrol.vx v10, v9, a0, v0.t
-# CHECK-INST: vrol.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 45 95 54 <unknown>
-
-vror.vv v10, v9, v8, v0.t
-# CHECK-INST: vror.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 05 94 50 <unknown>
-
-vror.vx v10, v9, a0, v0.t
-# CHECK-INST: vror.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 45 95 50 <unknown>
-
-vror.vi v10, v9, 33, v0.t
-# CHECK-INST: vror.vi v10, v9, 33, v0.t
-# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
-# CHECK-UNKNOWN: 57 b5 90 54 <unknown>
-
vwsll.vv v10, v9, v8, v0.t
# CHECK-INST: vwsll.vv v10, v9, v8, v0.t
# CHECK-ENCODING: [0x57,0x05,0x94,0xd4]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 05 94 d4 <unknown>
vwsll.vx v10, v9, a0, v0.t
# CHECK-INST: vwsll.vx v10, v9, a0, v0.t
# CHECK-ENCODING: [0x57,0x45,0x95,0xd4]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 45 95 d4 <unknown>
vwsll.vi v10, v9, 29, v0.t
# CHECK-INST: vwsll.vi v10, v9, 29, v0.t
# CHECK-ENCODING: [0x57,0xb5,0x9e,0xd4]
-# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions.){{$}}
# CHECK-UNKNOWN: 57 b5 9e d4 <unknown>
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -112,22 +112,25 @@
# CHECK: attribute 5, "rv32i2p1_zbc1p0"
.attribute arch, "rv32i_zve64x_zvbb1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvbc1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve32x_zvkb1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
+
.attribute arch, "rv32i_zve32x_zvkg1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvkn1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvknc1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvkng1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvknha1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
@@ -139,13 +142,13 @@
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvks1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvksc1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve64x_zvksg1p0"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvksed1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/rvv/vror.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vror.ll
+++ llvm/test/CodeGen/RISCV/rvv/vror.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8(
Index: llvm/test/CodeGen/RISCV/rvv/vrol.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vrol.ll
+++ llvm/test/CodeGen/RISCV/rvv/vrol.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8(
Index: llvm/test/CodeGen/RISCV/rvv/vrev8.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vrev8.ll
+++ llvm/test/CodeGen/RISCV/rvv/vrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8(
Index: llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
+++ llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8(
Index: llvm/test/CodeGen/RISCV/rvv/vandn.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vandn.ll
+++ llvm/test/CodeGen/RISCV/rvv/vandn.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8(
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -66,6 +66,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
@@ -155,6 +156,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
@@ -242,19 +244,20 @@
; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
-; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
-; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
-; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
@@ -330,19 +333,20 @@
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
-; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
-; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
-; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
-; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -110,15 +110,10 @@
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZvbb] in {
- defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;
- def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
def VBREV_V : VALUVs2<0b010010, 0b01010, OPMVV, "vbrev.v">;
def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">;
def VCPOP_V : VALUVs2<0b010010, 0b01110, OPMVV, "vcpop.v">;
def VCTZ_V : VALUVs2<0b010010, 0b01101, OPMVV, "vctz.v">;
- def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
- defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
- defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>;
} // Predicates = [HasStdExtZvbb]
@@ -128,6 +123,14 @@
defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>;
} // Predicates = [HasStdExtZvbc]
+let Predicates = [HasStdExtZvkb] in {
+ defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;
+ def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
+ def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
+ defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
+ defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
+} // Predicates = [HasStdExtZvkb]
+
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">;
def VGMUL_VV : PALUVs2NoVm<0b101000, 0b10001, OPMVV, "vgmul.vv">;
@@ -352,15 +355,10 @@
}
let Predicates = [HasStdExtZvbb] in {
- defm PseudoVANDN : VPseudoVALU_VV_VX;
defm PseudoVBREV : VPseudoVALU_V;
- defm PseudoVBREV8 : VPseudoVALU_V;
- defm PseudoVREV8 : VPseudoVALU_V;
defm PseudoVCLZ : VPseudoVALU_V;
defm PseudoVCTZ : VPseudoVALU_V;
defm PseudoVCPOP : VPseudoVALU_V;
- defm PseudoVROL : VPseudoVALU_VV_VX;
- defm PseudoVROR : VPseudoVALU_VV_VX_VI<uimm6>;
defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5>;
} // Predicates = [HasStdExtZvbb]
@@ -369,6 +367,14 @@
defm PseudoVCLMULH : VPseudoVCLMUL_VV_VX;
} // Predicates = [HasStdExtZvbc]
+let Predicates = [HasStdExtZvkb] in {
+ defm PseudoVANDN : VPseudoVALU_VV_VX;
+ defm PseudoVBREV8 : VPseudoVALU_V;
+ defm PseudoVREV8 : VPseudoVALU_V;
+ defm PseudoVROL : VPseudoVALU_VV_VX;
+ defm PseudoVROR : VPseudoVALU_VV_VX_VI<uimm6>;
+} // Predicates = [HasStdExtZvkb]
+
let Predicates = [HasStdExtZvkg] in {
defm PseudoVGHSH : VPseudoVALU_VV_NoMask_Zvk;
defm PseudoVGMUL : VPseudoVALU_V_NoMask_Zvk;
@@ -832,15 +838,10 @@
VPatBinaryW_VI_VWSLL<intrinsic, instruction, vtilist>;
let Predicates = [HasStdExtZvbb] in {
- defm : VPatBinaryV_VV_VX<"int_riscv_vandn", "PseudoVANDN", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vbrev", "PseudoVBREV", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vclz", "PseudoVCLZ", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vctz", "PseudoVCTZ", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vcpopv", "PseudoVCPOP", AllIntegerVectors>;
- defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;
- defm : VPatBinaryV_VV_VX_VI_VROR<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
defm : VPatBinaryW_VV_VX_VI_VWSLL<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors>;
} // Predicates = [HasStdExtZvbb]
@@ -849,6 +850,14 @@
defm : VPatBinaryV_VV_VX<"int_riscv_vclmulh", "PseudoVCLMULH", I64IntegerVectors>;
} // Predicates = [HasStdExtZvbc]
+let Predicates = [HasStdExtZvkb] in {
+ defm : VPatBinaryV_VV_VX<"int_riscv_vandn", "PseudoVANDN", AllIntegerVectors>;
+ defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;
+ defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;
+ defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;
+ defm : VPatBinaryV_VV_VX_VI_VROR<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
+} // Predicates = [HasStdExtZvkb]
+
let Predicates = [HasStdExtZvkg] in {
defm : VPatBinaryV_VV_NoMask<"int_riscv_vghsh", "PseudoVGHSH", I32IntegerVectors>;
defm : VPatUnaryV_V_NoMask_Zvk<"int_riscv_vgmul", "PseudoVGMUL", I32IntegerVectors>;
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -550,12 +550,20 @@
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
+def FeatureStdExtZvkb
+ : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkb),
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+
def FeatureStdExtZvbb
: SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
- "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+ "'Zvbb' (Vector basic bit-manipulation instructions.)",
+ [FeatureStdExtZvkb]>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
- "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+ "'Zvbb' (Vector basic bit-manipulation instructions.)">;
def FeatureStdExtZvbc
: SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
@@ -613,9 +621,9 @@
def FeatureStdExtZvkn
: SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
"This extension is shorthand for the following set of "
- "other extensions: Zvkned, Zvknhb, Zvbb and Zvkt.",
+ "other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvbb, FeatureStdExtZvkt]>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
: SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
@@ -632,9 +640,9 @@
def FeatureStdExtZvks
: SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
"This extension is shorthand for the following set of "
- "other extensions: Zvksed, Zvksh, Zvbb and Zvkt.",
+ "other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvbb, FeatureStdExtZvkt]>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
: SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -180,6 +180,7 @@
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
// vector crypto
+ {"zvkb", RISCVExtensionVersion{1, 0}},
{"zvkg", RISCVExtensionVersion{1, 0}},
{"zvkn", RISCVExtensionVersion{1, 0}},
{"zvknc", RISCVExtensionVersion{1, 0}},
@@ -975,6 +976,7 @@
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
"zkne", "zknd", "zknh"};
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
+static const char *ImpliedExtsZvbb[] = {"zvkb"};
static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
@@ -983,11 +985,11 @@
static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
-static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"};
+static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
static const char *ImpliedExtsZvknhb[] = {"zvknha"};
-static const char *ImpliedExtsZvks[] = {"zvbb", "zvksed", "zvksh", "zvkt"};
+static const char *ImpliedExtsZvks[] = {"zvkb", "zvksed", "zvksh", "zvkt"};
static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
@@ -1040,6 +1042,7 @@
{{"zk"}, {ImpliedExtsZk}},
{{"zkn"}, {ImpliedExtsZkn}},
{{"zks"}, {ImpliedExtsZks}},
+ {{"zvbb"}, {ImpliedExtsZvbb}},
{{"zve32f"}, {ImpliedExtsZve32f}},
{{"zve32x"}, {ImpliedExtsZve32x}},
{{"zve64d"}, {ImpliedExtsZve64d}},
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1830,16 +1830,18 @@
// These intrinsics will lower directly into the corresponding instructions
// added by the vector cyptography extension, if the extension is present.
let TargetPrefix = "riscv" in {
- // Zvbb
+ // Zvkb
defm vandn : RISCVBinaryAAX;
- defm vbrev : RISCVUnaryAA;
defm vbrev8 : RISCVUnaryAA;
defm vrev8 : RISCVUnaryAA;
+ defm vrol : RISCVBinaryAAX;
+ defm vror : RISCVBinaryAAX;
+
+ // Zvbb
+ defm vbrev : RISCVUnaryAA;
defm vclz : RISCVUnaryAA;
defm vctz : RISCVUnaryAA;
defm vcpopv : RISCVUnaryAA;
- defm vrol : RISCVBinaryAAX;
- defm vror : RISCVBinaryAAX;
defm vwsll : RISCVBinaryABX;
// Zvbc
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -211,8 +211,8 @@
``experimental-ztso``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
-``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
- LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
+ LLVM implements the `1.0.0-rc2 specification <https://github.com/riscv/riscv-crypto/releases/download/v/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
+// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -2874,16 +2874,18 @@
["vx", "Uw", "UwUvz"]]>;
let UnMaskedPolicyScheme = HasPassthruOperand in {
- // zvbb
+ // zvkb
defm vandn : RVVUnsignedBinBuiltinSet;
- defm vbrev : RVVOutBuiltinSetZvbb;
defm vbrev8 : RVVOutBuiltinSetZvbb;
defm vrev8 : RVVOutBuiltinSetZvbb;
+ defm vrol : RVVUnsignedShiftBuiltinSet;
+ defm vror : RVVUnsignedShiftBuiltinSet;
+
+ // zvbb
+ defm vbrev : RVVOutBuiltinSetZvbb;
defm vclz : RVVOutBuiltinSetZvbb;
defm vctz : RVVOutBuiltinSetZvbb;
defm vcpopv : RVVOutBuiltinSetZvbb;
- defm vrol : RVVUnsignedShiftBuiltinSet;
- defm vror : RVVUnsignedShiftBuiltinSet;
let OverloadedName = "vwsll" in
defm vwsll : RVVSignedWidenBinBuiltinSetVwsll;
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