Author: wangpc Date: 2023-08-10T20:41:44+08:00 New Revision: 5a3753f35632f8fd7920c5c99b1237113b5c435e
URL: https://github.com/llvm/llvm-project/commit/5a3753f35632f8fd7920c5c99b1237113b5c435e DIFF: https://github.com/llvm/llvm-project/commit/5a3753f35632f8fd7920c5c99b1237113b5c435e.diff LOG: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet We need unsigned integer here. Fixes #64534 Reviewed By: eopXD Differential Revision: https://reviews.llvm.org/D157476 Added: Modified: clang/include/clang/Basic/riscv_vector.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 0b598a71c9a3b3..6e737826f17339 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -125,7 +125,7 @@ multiclass RVVInt64BinBuiltinSet multiclass RVVSlideOneBuiltinSet : RVVOutOp1BuiltinSet<NAME, "csil", [["vx", "v", "vve"], - ["vx", "Uv", "UvUve"]]>; + ["vx", "Uv", "UvUvUe"]]>; multiclass RVVSignedShiftBuiltinSet : RVVOutOp1BuiltinSet<NAME, "csil", _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
