Author: Craig Topper Date: 2023-07-31T17:34:38-07:00 New Revision: 690edeab78ba6996a44f6fd9e8fce79cb78e7737
URL: https://github.com/llvm/llvm-project/commit/690edeab78ba6996a44f6fd9e8fce79cb78e7737 DIFF: https://github.com/llvm/llvm-project/commit/690edeab78ba6996a44f6fd9e8fce79cb78e7737.diff LOG: [AArch64] Remove copy/pasted RISC-V extension names from some tests. NFC Added: Modified: clang/test/Sema/aarch64-sve-vector-exp-ops.c clang/test/Sema/aarch64-sve-vector-log-ops.c clang/test/Sema/aarch64-sve-vector-pow-ops.c clang/test/Sema/aarch64-sve-vector-trig-ops.c Removed: ################################################################################ diff --git a/clang/test/Sema/aarch64-sve-vector-exp-ops.c b/clang/test/Sema/aarch64-sve-vector-exp-ops.c index 2b17442cc2cd13..f2bba8c7eeb196 100644 --- a/clang/test/Sema/aarch64-sve-vector-exp-ops.c +++ b/clang/test/Sema/aarch64-sve-vector-exp-ops.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \ -// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \ +// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify // REQUIRES: aarch64-registered-target #include <arm_sve.h> diff --git a/clang/test/Sema/aarch64-sve-vector-log-ops.c b/clang/test/Sema/aarch64-sve-vector-log-ops.c index 493e919a3f5049..2beb616c1edb16 100644 --- a/clang/test/Sema/aarch64-sve-vector-log-ops.c +++ b/clang/test/Sema/aarch64-sve-vector-log-ops.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \ -// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \ +// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify // REQUIRES: aarch64-registered-target #include <arm_sve.h> diff --git a/clang/test/Sema/aarch64-sve-vector-pow-ops.c b/clang/test/Sema/aarch64-sve-vector-pow-ops.c index 1024cdc2517d07..e61d752911fc3d 100644 --- a/clang/test/Sema/aarch64-sve-vector-pow-ops.c +++ b/clang/test/Sema/aarch64-sve-vector-pow-ops.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +experimental-zvfh \ -// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \ +// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify // REQUIRES: aarch64-registered-target #include <arm_sve.h> diff --git a/clang/test/Sema/aarch64-sve-vector-trig-ops.c b/clang/test/Sema/aarch64-sve-vector-trig-ops.c index 6d71088f9f540e..7ca941f578c70d 100644 --- a/clang/test/Sema/aarch64-sve-vector-trig-ops.c +++ b/clang/test/Sema/aarch64-sve-vector-trig-ops.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \ -// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \ +// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify // REQUIRES: aarch64-registered-target #include <arm_sve.h> _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
