SixWeining created this revision. SixWeining added reviewers: xen0n, xry111, hev, wangleiat. Herald added a project: All. SixWeining requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits.
Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D156195 Files: clang/docs/ReleaseNotes.rst llvm/docs/ReleaseNotes.rst Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -199,9 +199,13 @@ Changes to the LoongArch Backend -------------------------------- +* Adds assembler/disassembler support for the ``LSX``, ``LASX``, ``LVZ`` and + ``LBT`` ISA extensions. * The ``lp64s`` ABI is supported now and has been tested on Rust bare-matal target. * A target feature ``ual`` is introduced to allow unaligned memory accesses and this feature is enabled by default for generic 64-bit processors. +* Adds support for the ``large`` code model. +* Several codegen improvements are made. Changes to the MIPS Backend --------------------------- Index: clang/docs/ReleaseNotes.rst =================================================================== --- clang/docs/ReleaseNotes.rst +++ clang/docs/ReleaseNotes.rst @@ -891,6 +891,8 @@ on LoongArch. - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- Non ``$``-prefixed GPR names (e.g. ``r4`` and ``a0``) are allowed in inlineasm + like GCC does. RISC-V Support ^^^^^^^^^^^^^^
Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -199,9 +199,13 @@ Changes to the LoongArch Backend -------------------------------- +* Adds assembler/disassembler support for the ``LSX``, ``LASX``, ``LVZ`` and + ``LBT`` ISA extensions. * The ``lp64s`` ABI is supported now and has been tested on Rust bare-matal target. * A target feature ``ual`` is introduced to allow unaligned memory accesses and this feature is enabled by default for generic 64-bit processors. +* Adds support for the ``large`` code model. +* Several codegen improvements are made. Changes to the MIPS Backend --------------------------- Index: clang/docs/ReleaseNotes.rst =================================================================== --- clang/docs/ReleaseNotes.rst +++ clang/docs/ReleaseNotes.rst @@ -891,6 +891,8 @@ on LoongArch. - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- Non ``$``-prefixed GPR names (e.g. ``r4`` and ``a0``) are allowed in inlineasm + like GCC does. RISC-V Support ^^^^^^^^^^^^^^
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