SixWeining added inline comments.
================
Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:56
addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
+ if (Subtarget.hasExtLSX()) {
+ for (auto VT : {MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32,
----------------
useless brace
================
Comment at: llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll:40
+
+;; The lower 64-bit of the vector register '$xr31' is same as the
+;; floating-point register '$f31' ('$fs7'). And '$f31' ('$fs7')
----------------
`overlapped with` is more accurate.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154931/new/
https://reviews.llvm.org/D154931
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