craig.topper added inline comments.
================ Comment at: clang/lib/Sema/SemaChecking.cpp:4576 + case RISCVVector::BI__builtin_rvv_vaeskf1_vi_ta: + case RISCVVector::BI__builtin_rvv_vsm4k_vi_ta: + return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); ---------------- eopXD wrote: > Valid range of `vaeskf1`, `vaeskf2` seems to be 0 to 15. [0] > Valid range of `vsm4k` seems to be 0 to 7 [1]. > > > > [0] > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vaeskf1.adoc > > [1] > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vsm4k.adoc I think the field in the instruction is 5 bits, but vaeskf1 and vaeskf2 ignore bit 4. The true valid range is 1-10. The other values are aliased to one of the valid values. Should the intrinsic interface expose all 32 possible values or just 1-10? ================ Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:12 +// +vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) { + return __riscv_vwsll_vv_i16mf4(op1, op2, vl); ---------------- It doesn't make sense for op2 to be signed. It's a shift amount, its always a positive number ================ Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:22 +// +vint16mf4_t test_vwsll_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) { + return __riscv_vwsll_vx_i16mf4(op1, op2, vl); ---------------- scalar shift amounts should be size_t Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138810/new/ https://reviews.llvm.org/D138810 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
