FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
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FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.
For more details about these instructions, please refer to the latest ISE
document:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D155147
Files:
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/BuiltinsX86.def
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/X86.cpp
clang/lib/Basic/Targets/X86.h
clang/lib/Headers/CMakeLists.txt
clang/lib/Headers/immintrin.h
clang/lib/Headers/sm3intrin.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/X86/sm3-builtins.c
clang/test/CodeGen/X86/sm3-error.c
clang/test/CodeGen/attr-target-x86.c
clang/test/Driver/x86-target-features.c
clang/test/Preprocessor/x86_target_features.c
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/include/llvm/TargetParser/X86TargetParser.def
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/TargetParser/Host.cpp
llvm/lib/TargetParser/X86TargetParser.cpp
llvm/test/CodeGen/X86/sm3-intrinsics.ll
llvm/test/MC/Disassembler/X86/sm3-32.txt
llvm/test/MC/Disassembler/X86/sm3-64.txt
llvm/test/MC/X86/sm3-att-32.s
llvm/test/MC/X86/sm3-att-64.s
llvm/test/MC/X86/sm3-intel-32.s
llvm/test/MC/X86/sm3-intel-64.s
Index: llvm/test/MC/X86/sm3-intel-64.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x15,0x00,0x00,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [rip], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [rdx - 2048], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [rdx - 2048], 123
+
Index: llvm/test/MC/X86/sm3-intel-32.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-32.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+
Index: llvm/test/MC/X86/sm3-att-64.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/sm3-att-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg1 268435456(%rbp,%r14,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg1 268435456(%rbp,%r14,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 291(%r8,%rax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg1 291(%r8,%rax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 (%rip), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+ vsm3msg1 (%rip), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -512(,%rbp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 -512(,%rbp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 2032(%rcx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 2032(%rcx), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -2048(%rdx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 -2048(%rdx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg2 268435456(%rbp,%r14,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg2 268435456(%rbp,%r14,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 291(%r8,%rax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg2 291(%r8,%rax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 (%rip), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+ vsm3msg2 (%rip), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -512(,%rbp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 -512(,%rbp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 2032(%rcx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 2032(%rcx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -2048(%rdx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 -2048(%rdx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 291(%r8,%rax,4), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, (%rip), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x15,0x00,0x00,0x00,0x00,0x7b]
+ vsm3rnds2 $123, (%rip), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -512(,%rbp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -512(,%rbp,2), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 2032(%rcx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 2032(%rcx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -2048(%rdx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -2048(%rdx), %xmm3, %xmm2
+
Index: llvm/test/MC/X86/sm3-att-32.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/sm3-att-32.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+ vsm3msg1 (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 -2048(%edx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+ vsm3msg2 (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 -2048(%edx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+ vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+
Index: llvm/test/MC/Disassembler/X86/sm3-64.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sm3-64.txt
@@ -0,0 +1,90 @@
+
+# isadb version: 6aa5c837365e1d1e6e53b3fc3d95ab184e9c06eb
+
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmm4
+0xc4,0xe2,0x60,0xda,0xd4
+
+# ATT: vsm3msg1 268435456(%rbp,%r14,8), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg1 291(%r8,%rax,4), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg1 (%rip), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00
+
+# ATT: vsm3msg1 -512(,%rbp,2), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg1 2032(%rcx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg1 -2048(%rdx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmm4
+0xc4,0xe2,0x61,0xda,0xd4
+
+# ATT: vsm3msg2 268435456(%rbp,%r14,8), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg2 291(%r8,%rax,4), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg2 (%rip), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00
+
+# ATT: vsm3msg2 -512(,%rbp,2), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg2 2032(%rcx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg2 -2048(%rdx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123
+0xc4,0xe3,0x61,0xde,0xd4,0x7b
+
+# ATT: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, (%rip), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [rip], 123
+0xc4,0xe3,0x61,0xde,0x15,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -512(,%rbp,2), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*rbp - 512], 123
+0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vsm3rnds2 $123, 2032(%rcx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [rcx + 2032], 123
+0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -2048(%rdx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [rdx - 2048], 123
+0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b
+
Index: llvm/test/MC/Disassembler/X86/sm3-32.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sm3-32.txt
@@ -0,0 +1,88 @@
+
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmm4
+0xc4,0xe2,0x60,0xda,0xd4
+
+# ATT: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg1 (%eax), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x60,0xda,0x10
+
+# ATT: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg1 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg1 -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmm4
+0xc4,0xe2,0x61,0xda,0xd4
+
+# ATT: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg2 (%eax), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x61,0xda,0x10
+
+# ATT: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg2 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg2 -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123
+0xc4,0xe3,0x61,0xde,0xd4,0x7b
+
+# ATT: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+0xc4,0xe3,0x61,0xde,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b
+
Index: llvm/test/CodeGen/X86/sm3-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/sm3-intrinsics.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+
+define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3rnds2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)
+
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===================================================================
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -613,6 +613,7 @@
constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
+constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
// AVX512 features.
constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
Index: llvm/lib/TargetParser/Host.cpp
===================================================================
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -1746,6 +1746,7 @@
Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
bool HasLeaf7Subleaf1 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
+ Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
Index: llvm/lib/Target/X86/X86InstrSSE.td
===================================================================
--- llvm/lib/Target/X86/X86InstrSSE.td
+++ llvm/lib/Target/X86/X86InstrSSE.td
@@ -8295,3 +8295,43 @@
(VCVTNEPS2BF16rr VR128:$dst, VR128:$src), 0, "att">;
def : InstAlias<"vcvtneps2bf16y\t{$src, $dst|$dst, $src}",
(VCVTNEPS2BF16Yrr VR128:$dst, VR256:$src), 0, "att">;
+
+let Predicates = [HasSM3], Constraints = "$src1 = $dst" in {
+ multiclass SM3_Base<string OpStr> {
+ def rr : I<0xda, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, VR128:$src3),
+ !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ [(set VR128:$dst,
+ (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+ VR128:$src2, VR128:$src3))]>,
+ Sched<[WriteVecIMul]>, VEX_4V;
+ def rm : I<0xda, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i128mem:$src3),
+ !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ [(set VR128:$dst,
+ (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+ VR128:$src2, (loadv4i32 addr:$src3)))]>,
+ Sched<[WriteVecIMul]>, VEX_4V;
+ }
+
+ multiclass VSM3RNDS2_Base {
+ def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4),
+ "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+ [(set VR128:$dst,
+ (int_x86_vsm3rnds2 VR128:$src1,
+ VR128:$src2, VR128:$src3, timm:$src4))]>,
+ Sched<[WriteVecIMul]>;
+ def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4),
+ "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+ [(set VR128:$dst,
+ (int_x86_vsm3rnds2 VR128:$src1,
+ VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+ Sched<[WriteVecIMul]>;
+ }
+}
+
+defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS;
+defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD;
+defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD;
Index: llvm/lib/Target/X86/X86InstrInfo.td
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -968,6 +968,7 @@
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
+def HasSM3 : Predicate<"Subtarget->hasSM3()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -242,6 +242,9 @@
// using Shadow Stack
def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
"Support CET Shadow-Stack instructions">;
+def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true",
+ "Support SM3 instructions",
+ [FeatureAVX]>;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
Index: llvm/include/llvm/TargetParser/X86TargetParser.def
===================================================================
--- llvm/include/llvm/TargetParser/X86TargetParser.def
+++ llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -221,6 +221,7 @@
X86_FEATURE (HRESET, "hreset")
X86_FEATURE (RAOINT, "raoint")
X86_FEATURE (AVX512FP16, "avx512fp16")
+X86_FEATURE (SM3, "sm3")
X86_FEATURE (AMX_FP16, "amx-fp16")
X86_FEATURE (CMPCCXADD, "cmpccxadd")
X86_FEATURE (AVXNECONVERT, "avxneconvert")
Index: llvm/include/llvm/IR/IntrinsicsX86.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsX86.td
+++ llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5513,6 +5513,25 @@
DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8f32_ty], [IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
+// SM3 intrinsics
+let TargetPrefix = "x86" in {
+ def int_x86_vsm3msg1
+ : ClangBuiltin<"__builtin_ia32_vsm3msg1">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+ def int_x86_vsm3msg2
+ : ClangBuiltin<"__builtin_ia32_vsm3msg2">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+ def int_x86_vsm3rnds2
+ : ClangBuiltin<"__builtin_ia32_vsm3rnds2">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<3>>, IntrNoMem]>;
+}
+//===----------------------------------------------------------------------===//
// RAO-INT intrinsics
let TargetPrefix = "x86" in {
def int_x86_aadd32
Index: llvm/docs/ReleaseNotes.rst
===================================================================
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -276,7 +276,7 @@
* ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend.
``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
-
+* Support ISA of ``SM3``.
Changes to the OCaml bindings
-----------------------------
Index: clang/test/Preprocessor/x86_target_features.c
===================================================================
--- clang/test/Preprocessor/x86_target_features.c
+++ clang/test/Preprocessor/x86_target_features.c
@@ -660,6 +660,20 @@
// AVXNECONVERTNOAVX2-NOT: #define __AVX2__ 1
// AVXNECONVERTNOAVX2-NOT: #define __AVXNECONVERT__ 1
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -x c -E -dM -o - %s | FileCheck -check-prefix=SM3 %s
+
+// SM3: #define __AVX__ 1
+// SM3: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm3 -x c -E -dM -o - %s | FileCheck -check-prefix=NOSM3 %s
+
+// NOSM3-NOT: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck -check-prefix=SM3NOAVX %s
+
+// SM3NOAVX-NOT: #define __SM3__ 1
+// SM3NOAVX-NOT: #define __AVX__ 1
+
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
// CRC32: #define __CRC32__ 1
Index: clang/test/Driver/x86-target-features.c
===================================================================
--- clang/test/Driver/x86-target-features.c
+++ clang/test/Driver/x86-target-features.c
@@ -349,6 +349,11 @@
// AVXNECONVERT: "-target-feature" "+avxneconvert"
// NO-AVXNECONVERT: "-target-feature" "-avxneconvert"
+// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
+// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
+// SM3: "-target-feature" "+sm3"
+// NO-SM3: "-target-feature" "-sm3"
+
// RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
// RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
// CRC32: "-target-feature" "+crc32"
Index: clang/test/CodeGen/attr-target-x86.c
===================================================================
--- clang/test/CodeGen/attr-target-x86.c
+++ clang/test/CodeGen/attr-target-x86.c
@@ -54,9 +54,9 @@
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
// CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
+// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
// CHECK-NOT: tune-cpu
// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
Index: clang/test/CodeGen/X86/sm3-error.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/X86/sm3-error.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3 -emit-llvm -fsyntax-only -verify
+
+#include <immintrin.h>
+#include <stddef.h>
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
Index: clang/test/CodeGen/X86/sm3-builtins.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/X86/sm3-builtins.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+#include <stddef.h>
+
+__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3msg1_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+ return _mm_sm3msg1_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3msg2_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+ return _mm_sm3msg2_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3rnds2_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127)
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 127);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===================================================================
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -5864,6 +5864,7 @@
case X86::BI__builtin_ia32_pternlogq128_maskz:
case X86::BI__builtin_ia32_pternlogq256_mask:
case X86::BI__builtin_ia32_pternlogq256_maskz:
+ case X86::BI__builtin_ia32_vsm3rnds2:
i = 3; l = 0; u = 255;
break;
case X86::BI__builtin_ia32_gatherpfdpd:
Index: clang/lib/Headers/sm3intrin.h
===================================================================
--- /dev/null
+++ clang/lib/Headers/sm3intrin.h
@@ -0,0 +1,40 @@
+/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SM3INTRIN_H
+#define __SM3INTRIN_H
+
+#define __DEFAULT_FN_ATTRS128 \
+ __attribute__((__always_inline__, __nodebug__, __target__("sm3"), \
+ __min_vector_width__(128)))
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
+ __m128i __B,
+ __m128i __C) {
+ return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
+ (__v4su)__C);
+}
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
+ __m128i __B,
+ __m128i __C) {
+ return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
+ (__v4su)__C);
+}
+
+#define _mm_sm3rnds2_epi32(A, B, C, D) \
+ (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
+
+#undef __DEFAULT_FN_ATTRS128
+
+#endif // __SM3INTRIN_H
Index: clang/lib/Headers/immintrin.h
===================================================================
--- clang/lib/Headers/immintrin.h
+++ clang/lib/Headers/immintrin.h
@@ -269,6 +269,11 @@
#include <avxneconvertintrin.h>
#endif
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
+ defined(__SM3__)
+#include <sm3intrin.h>
+#endif
+
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
defined(__RDPID__)
/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
Index: clang/lib/Headers/CMakeLists.txt
===================================================================
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -204,6 +204,7 @@
serializeintrin.h
sgxintrin.h
shaintrin.h
+ sm3intrin.h
smmintrin.h
tbmintrin.h
tmmintrin.h
Index: clang/lib/Basic/Targets/X86.h
===================================================================
--- clang/lib/Basic/Targets/X86.h
+++ clang/lib/Basic/Targets/X86.h
@@ -113,6 +113,7 @@
bool HasAVX512VP2INTERSECT = false;
bool HasSHA = false;
bool HasSHSTK = false;
+ bool HasSM3 = false;
bool HasSGX = false;
bool HasCX8 = false;
bool HasCX16 = false;
Index: clang/lib/Basic/Targets/X86.cpp
===================================================================
--- clang/lib/Basic/Targets/X86.cpp
+++ clang/lib/Basic/Targets/X86.cpp
@@ -263,6 +263,8 @@
HasSHA = true;
} else if (Feature == "+shstk") {
HasSHSTK = true;
+ } else if (Feature == "+sm3") {
+ HasSM3 = true;
} else if (Feature == "+movbe") {
HasMOVBE = true;
} else if (Feature == "+sgx") {
@@ -772,6 +774,8 @@
Builder.defineMacro("__SHSTK__");
if (HasSGX)
Builder.defineMacro("__SGX__");
+ if (HasSM3)
+ Builder.defineMacro("__SM3__");
if (HasPREFETCHI)
Builder.defineMacro("__PREFETCHI__");
if (HasPREFETCHWT1)
@@ -1000,6 +1004,7 @@
.Case("sgx", true)
.Case("sha", true)
.Case("shstk", true)
+ .Case("sm3", true)
.Case("sse", true)
.Case("sse2", true)
.Case("sse3", true)
@@ -1105,6 +1110,7 @@
.Case("sgx", HasSGX)
.Case("sha", HasSHA)
.Case("shstk", HasSHSTK)
+ .Case("sm3", HasSM3)
.Case("sse", SSELevel >= SSE1)
.Case("sse2", SSELevel >= SSE2)
.Case("sse3", SSELevel >= SSE3)
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5043,6 +5043,8 @@
def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>;
def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
+def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
+def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
Index: clang/include/clang/Basic/BuiltinsX86.def
===================================================================
--- clang/include/clang/Basic/BuiltinsX86.def
+++ clang/include/clang/Basic/BuiltinsX86.def
@@ -2141,6 +2141,11 @@
TARGET_HEADER_BUILTIN(_InterlockedOr64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_InterlockedXor64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+// SM3
+TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
+
#undef BUILTIN
#undef TARGET_BUILTIN
#undef TARGET_HEADER_BUILTIN
Index: clang/docs/ReleaseNotes.rst
===================================================================
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -700,6 +700,10 @@
- Add ISA of ``AMX-COMPLEX`` which supports ``tcmmimfp16ps`` and
``tcmmrlfp16ps``.
+- Support ISA of ``SM3``.
+ * Support intrinsic of ``_mm_sm3msg1_epi32``.
+ * Support intrinsic of ``_mm_sm3msg2_epi32``.
+ * Support intrinsic of ``_mm_sm3rnds2_epi32``.
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
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