[PATCH] D154636: [8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6821
 
//===----------------------------------------------------------------------===//
-let Uses = [FRM], mayRaiseFPException = true in {
-defm PseudoVFREDOSUM : VPseudoVFREDO_VS;
-defm PseudoVFREDUSUM : VPseudoVFRED_VS;
+let mayRaiseFPException = true,
+    hasSideEffects = 0 in {
----------------
One line


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6834
 
//===----------------------------------------------------------------------===//
 let IsRVVWideningReduction = 1,
+    hasSideEffects = 0,
----------------
One or two lines, not 3.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154636/new/

https://reviews.llvm.org/D154636

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits