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Allow _32 builtin on RV64 since it only brev8+sext.w.
Part of an effort to remove 'long' to mean XLen from the builtin
interface.
Matches the proposal here
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D154683
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
@@ -2,7 +2,20 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBKB
-// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT: entry:
+// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32
[[TMP0]])
+// RV64ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int brev8_32(int rs1)
+{
+ return __builtin_riscv_brev8_32(rs1);
+}
+
+// RV64ZBKB-LABEL: @brev8_64(
// RV64ZBKB-NEXT: entry:
// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKB-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
@@ -10,7 +23,7 @@
// RV64ZBKB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.brev8.i64(i64
[[TMP0]])
// RV64ZBKB-NEXT: ret i64 [[TMP1]]
//
-long brev8(long rs1)
+long brev8_64(long rs1)
{
- return __builtin_riscv_brev8(rs1);
+ return __builtin_riscv_brev8_64(rs1);
}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
@@ -10,9 +10,9 @@
// RV32ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32
[[TMP0]])
// RV32ZBKB-NEXT: ret i32 [[TMP1]]
//
-long brev8(long rs1)
+int brev8(int rs1)
{
- return __builtin_riscv_brev8(rs1);
+ return __builtin_riscv_brev8_32(rs1);
}
// RV32ZBKB-LABEL: @zip(
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -20164,7 +20164,8 @@
case RISCV::BI__builtin_riscv_clmulr:
case RISCV::BI__builtin_riscv_xperm4:
case RISCV::BI__builtin_riscv_xperm8:
- case RISCV::BI__builtin_riscv_brev8:
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
case RISCV::BI__builtin_riscv_zip_32:
case RISCV::BI__builtin_riscv_unzip_32: {
switch (BuiltinID) {
@@ -20213,7 +20214,8 @@
break;
// Zbkb
- case RISCV::BI__builtin_riscv_brev8:
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
ID = Intrinsic::riscv_brev8;
break;
case RISCV::BI__builtin_riscv_zip_32:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -33,7 +33,8 @@
TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
// Zbkb extension
-TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_32, "ii", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_64, "WiWi", "nc", "zbkb,64bit")
TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
@@ -2,7 +2,20 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBKB
-// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT: entry:
+// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV64ZBKB-NEXT: ret i32 [[TMP1]]
+//
+int brev8_32(int rs1)
+{
+ return __builtin_riscv_brev8_32(rs1);
+}
+
+// RV64ZBKB-LABEL: @brev8_64(
// RV64ZBKB-NEXT: entry:
// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKB-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
@@ -10,7 +23,7 @@
// RV64ZBKB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[TMP0]])
// RV64ZBKB-NEXT: ret i64 [[TMP1]]
//
-long brev8(long rs1)
+long brev8_64(long rs1)
{
- return __builtin_riscv_brev8(rs1);
+ return __builtin_riscv_brev8_64(rs1);
}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
@@ -10,9 +10,9 @@
// RV32ZBKB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
// RV32ZBKB-NEXT: ret i32 [[TMP1]]
//
-long brev8(long rs1)
+int brev8(int rs1)
{
- return __builtin_riscv_brev8(rs1);
+ return __builtin_riscv_brev8_32(rs1);
}
// RV32ZBKB-LABEL: @zip(
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -20164,7 +20164,8 @@
case RISCV::BI__builtin_riscv_clmulr:
case RISCV::BI__builtin_riscv_xperm4:
case RISCV::BI__builtin_riscv_xperm8:
- case RISCV::BI__builtin_riscv_brev8:
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
case RISCV::BI__builtin_riscv_zip_32:
case RISCV::BI__builtin_riscv_unzip_32: {
switch (BuiltinID) {
@@ -20213,7 +20214,8 @@
break;
// Zbkb
- case RISCV::BI__builtin_riscv_brev8:
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
ID = Intrinsic::riscv_brev8;
break;
case RISCV::BI__builtin_riscv_zip_32:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -33,7 +33,8 @@
TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
// Zbkb extension
-TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_32, "ii", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_64, "WiWi", "nc", "zbkb,64bit")
TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
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