craig.topper created this revision. craig.topper added reviewers: Jim, asb. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson. Herald added a project: All. craig.topper requested review of this revision. Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay. Herald added a project: clang.
Inspried by D153235 <https://reviews.llvm.org/D153235>, I think bit manipulation makes more sense on unsigned types. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D153403 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -10,7 +10,7 @@ // RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) // RV64ZBB-NEXT: ret i32 [[TMP1]] // -int orc_b_32(int a) { +unsigned int orc_b_32(unsigned int a) { return __builtin_riscv_orc_b_32(a); } @@ -22,7 +22,7 @@ // RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]]) // RV64ZBB-NEXT: ret i64 [[TMP1]] // -long orc_b_64(long a) { +unsigned long orc_b_64(unsigned long a) { return __builtin_riscv_orc_b_64(a); } @@ -72,4 +72,4 @@ // long ctz_64(long a) { return __builtin_riscv_ctz_64(a); -} \ No newline at end of file +} Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -10,7 +10,7 @@ // RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) // RV32ZBB-NEXT: ret i32 [[TMP1]] // -int orc_b_32(int a) { +unsigned int orc_b_32(unsigned int a) { return __builtin_riscv_orc_b_32(a); } @@ -36,4 +36,4 @@ // int ctz_32(int a) { return __builtin_riscv_ctz_32(a); -} \ No newline at end of file +} Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o - -int orc_b_64(int a) { +unsigned int orc_b_64(unsigned int a) { return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires: 'RV64'}} } Index: clang/include/clang/Basic/BuiltinsRISCV.def =================================================================== --- clang/include/clang/Basic/BuiltinsRISCV.def +++ clang/include/clang/Basic/BuiltinsRISCV.def @@ -16,8 +16,8 @@ #endif // Zbb extension -TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb") -TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_orc_b_32, "UZiUZi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit") TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb") TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit") TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -10,7 +10,7 @@ // RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) // RV64ZBB-NEXT: ret i32 [[TMP1]] // -int orc_b_32(int a) { +unsigned int orc_b_32(unsigned int a) { return __builtin_riscv_orc_b_32(a); } @@ -22,7 +22,7 @@ // RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]]) // RV64ZBB-NEXT: ret i64 [[TMP1]] // -long orc_b_64(long a) { +unsigned long orc_b_64(unsigned long a) { return __builtin_riscv_orc_b_64(a); } @@ -72,4 +72,4 @@ // long ctz_64(long a) { return __builtin_riscv_ctz_64(a); -} \ No newline at end of file +} Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -10,7 +10,7 @@ // RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) // RV32ZBB-NEXT: ret i32 [[TMP1]] // -int orc_b_32(int a) { +unsigned int orc_b_32(unsigned int a) { return __builtin_riscv_orc_b_32(a); } @@ -36,4 +36,4 @@ // int ctz_32(int a) { return __builtin_riscv_ctz_32(a); -} \ No newline at end of file +} Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o - -int orc_b_64(int a) { +unsigned int orc_b_64(unsigned int a) { return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires: 'RV64'}} } Index: clang/include/clang/Basic/BuiltinsRISCV.def =================================================================== --- clang/include/clang/Basic/BuiltinsRISCV.def +++ clang/include/clang/Basic/BuiltinsRISCV.def @@ -16,8 +16,8 @@ #endif // Zbb extension -TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb") -TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_orc_b_32, "UZiUZi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit") TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb") TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit") TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
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