tra added inline comments.
================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:559-568
-multiclass CVT_FROM_FLOAT_SM80<string FromName, RegisterClass RC> {
- def _f32 :
- NVPTXInst<(outs RC:$dst),
- (ins Float32Regs:$src, CvtMode:$mode),
- !strconcat("cvt${mode:base}${mode:relu}.",
- FromName, ".f32 \t$dst, $src;"), []>,
- Requires<[hasPTX<70>, hasSM<80>]>;
----------------
This is where cvt.rn.relu.bf16.f32 was used to be generated before.
Now we've replaced it with `CVT_FROM_ALL` which does not know anything about
`relu`.
================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:595-596
FromName, ".f16 \t$dst, $src;"), []>;
+ def _bf16 :
+ NVPTXInst<(outs RC:$dst),
+ (ins Int16Regs:$src, CvtMode:$mode),
----------------
While we're here, it also needs `Requires<[hasPTX<70>, hasSM<80>]>`
================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:601
def _f32 :
NVPTXInst<(outs RC:$dst),
(ins Float32Regs:$src, CvtMode:$mode),
----------------
We may add an optional `list<Predicate>` argument to the multiclass and
do`defm CVT_bf16<... [hasPTX<70>, hasSM<80>]>`
================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:603
(ins Float32Regs:$src, CvtMode:$mode),
!strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
FromName, ".f32 \t$dst, $src;"), []>;
----------------
We also need to augment it with `${mode:relu}`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144911/new/
https://reviews.llvm.org/D144911
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