eopXD updated this revision to Diff 532536. eopXD added a comment. Herald added a subscriber: qcolombet.
Update code: - Change value to indicate no rounding mode change from `99` to `7`. - Add code under `RISCVDAGToDAGISel::performCombineVMergeAndVOps` to deal with the extra rounding mode operand - This patch was originally depending upon D152889 <https://reviews.llvm.org/D152889>, the patch is dropped and now this patch depends on D152879 <https://reviews.llvm.org/D152879>. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152996/new/ https://reviews.llvm.org/D152996 Files: clang/include/clang/Basic/riscv_vector.td clang/include/clang/Basic/riscv_vector_common.td clang/include/clang/Support/RISCVVIntrinsicUtils.h clang/lib/Sema/SemaRISCVVectorLookup.cpp clang/lib/Support/RISCVVIntrinsicUtils.cpp clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c clang/utils/TableGen/RISCVVEmitter.cpp llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp llvm/lib/Target/RISCV/RISCVInstrFormats.td llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll llvm/test/CodeGen/RISCV/rvv/masked-tama.ll llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll llvm/test/CodeGen/RISCV/rvv/vfadd.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
