abel-bernabeu added a comment. In D153008#4425244 <https://reviews.llvm.org/D153008#4425244>, @jrtc27 wrote:
> In D153008#4425238 <https://reviews.llvm.org/D153008#4425238>, @abel-bernabeu > wrote: > >> In D153008#4424821 <https://reviews.llvm.org/D153008#4424821>, @jrtc27 wrote: >> >>> Clang tests should not compile to asm. You want an IR test. >> >> Jessica, are there any exceptions for tests is under CodeGen/RISCV intended >> to exercise the assembly parser? >> >> I have just written a test that reproduces the way I manually test the >> feature. > > No. You can test the assembly parser just as easily from IR. > > I'll also note that your assembly isn't particularly minimal, which it should > be, unless the `add zero, %[dst], %[dst]` lines are doing something I'm not > aware of? Jessica, the LLVM IR form contains the inline assembly still unparsed. Look, this is what I get: abel@Docker:~/work/llvm-project/build$ ./bin/clang -fPIC --target=riscv64-unknown-elf -o - -S -emit-llvm ../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c ; ModuleID = '../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c' source_filename = "../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" target triple = "riscv64-unknown-unknown-elf" ; Function Attrs: noinline nounwind optnone define i64 @f() #0 { %1 = alloca i64, align 8 %2 = call i64 asm "li /* this is fine */ $0 , /* this is also fine */ 0 /* and last but not least */\0A", "=r"() #1, !srcloc !6 store i64 %2, ptr %1, align 8 %3 = load i64, ptr %1, align 8 ret i64 %3 } attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } attributes #1 = { nounwind memory(none) } !llvm.module.flags = !{!0, !1, !2, !3, !4} !llvm.ident = !{!5} !0 = !{i32 1, !"wchar_size", i32 4} !1 = !{i32 1, !"target-abi", !"lp64"} !2 = !{i32 8, !"PIC Level", i32 2} !3 = !{i32 7, !"frame-pointer", i32 2} !4 = !{i32 8, !"SmallDataLimit", i32 0} !5 = !{!"clang version 17.0.0 (g...@github.com:llvm/llvm-project.git 61bab164d4c3b15ba13ddd53de7bdeb6b8c9de30)"} !6 = !{i64 139} From the provided assembly template only the substituion of "%[dst]" for "$0" is observable on the LLVM IR. Am I misinterpreting your suggestion? Thanks in advance for you clarification. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153008/new/ https://reviews.llvm.org/D153008 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
