MaskRay accepted this revision. MaskRay added a comment. This revision is now accepted and ready to land.
Will be good to wait a few days to give regular RISC-V backend developers a chance to leave any final comments. ================ Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:332 + continue; + while (!isRegAvailable(NextReg)) + ++NextReg; ---------------- samitolvanen wrote: > MaskRay wrote: > > As a minor optimization to skip one redundant `isRegAvailable` call: `while > > (!isRegAvailable(++NextReg));` > `Reg` != `NextReg` here, and using `while (!isRegAvailable(++NextReg))` would > always skip the first alternative register by first incrementing `NextReg` > before calling `isRegsAvailable`. What am I missing? Ah you are right. Didn't notice the Reg/nextReg difference. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148385/new/ https://reviews.llvm.org/D148385 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
