Author: Hans Wennborg Date: 2023-06-12T17:18:09+02:00 New Revision: b18ca7296ef16700fadac98abe7fac8c8b44b4da
URL: https://github.com/llvm/llvm-project/commit/b18ca7296ef16700fadac98abe7fac8c8b44b4da DIFF: https://github.com/llvm/llvm-project/commit/b18ca7296ef16700fadac98abe7fac8c8b44b4da.diff LOG: Revert "[Driver] Mark many target-specific driver-only options as TargetSpecific" This broke building the TSan runtime on Mac, see comment on https://github.com/llvm/llvm-project/commit/5548843d692a92a7840f14002debc3cebcb3cdc3 > so that they get an error on other targets. This change uses let statements to > apply `Flags = [TargetSpecific]` to options (mostly -m*) without specifying > `Flags`. > Follow-up to D151590. > > For some options, e.g. -mdefault-build-attributes (D31813), -mbranch-likely > (D38168), -mfpu=/-mabi= (6890b9b71e525020ab58d436336664beede71575), a warning > seems desired in at least certain cases. This is not the best practice, but > this > change works around them by not applying `Flags = [TargetSpecific]`. > > ( > For Intel CPU errata -malign-branch= family options, we also drop the unneeded > NotXarchOption flag. This flag reports an error if the option is used with > -Xarch_*. This error reporting does not seem very useful. > ) This reverts commit 5548843d692a92a7840f14002debc3cebcb3cdc3. Added: Modified: clang/include/clang/Driver/Options.td clang/test/Driver/munaligned-access-unused.c clang/test/Driver/x86-malign-branch.c Removed: ################################################################################ diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 590787cb5da6e..dd98201d15201 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -251,10 +251,6 @@ def flang_ignored_w_Group : OptionGroup<"<flang ignored W group>">, def clang_ignored_legacy_options_Group : OptionGroup<"<clang legacy flags>">, Group<f_Group>, Flags<[Ignored]>; -def LongDouble_Group : OptionGroup<"<LongDouble group>">, Group<m_Group>, - DocName<"Long double flags">, - DocBrief<[{Selects the long double implementation}]>; - // Retired with clang-5.0 def : Flag<["-"], "fslp-vectorize-aggressive">, Group<clang_ignored_legacy_options_Group>; def : Flag<["-"], "fno-slp-vectorize-aggressive">, Group<clang_ignored_legacy_options_Group>; @@ -3512,39 +3508,36 @@ def mno_iamcu : Flag<["-"], "mno-iamcu">, Group<m_Group>, Flags<[NoXarchOption, def malign_functions_EQ : Joined<["-"], "malign-functions=">, Group<clang_ignored_m_Group>; def malign_loops_EQ : Joined<["-"], "malign-loops=">, Group<clang_ignored_m_Group>; def malign_jumps_EQ : Joined<["-"], "malign-jumps=">, Group<clang_ignored_m_Group>; - -let Flags = [TargetSpecific] in { -def malign_branch_EQ : CommaJoined<["-"], "malign-branch=">, Group<m_Group>, +def malign_branch_EQ : CommaJoined<["-"], "malign-branch=">, Group<m_Group>, Flags<[NoXarchOption]>, HelpText<"Specify types of branches to align">; -def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group<m_Group>, +def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group<m_Group>, Flags<[NoXarchOption]>, HelpText<"Specify the boundary's size to align branches">; -def mpad_max_prefix_size_EQ : Joined<["-"], "mpad-max-prefix-size=">, Group<m_Group>, +def mpad_max_prefix_size_EQ : Joined<["-"], "mpad-max-prefix-size=">, Group<m_Group>, Flags<[NoXarchOption]>, HelpText<"Specify maximum number of prefixes to use for padding">; -def mbranches_within_32B_boundaries : Flag<["-"], "mbranches-within-32B-boundaries">, Group<m_Group>, +def mbranches_within_32B_boundaries : Flag<["-"], "mbranches-within-32B-boundaries">, Flags<[NoXarchOption]>, Group<m_Group>, HelpText<"Align selected branches (fused, jcc, jmp) within 32-byte boundary">; def mfancy_math_387 : Flag<["-"], "mfancy-math-387">, Group<clang_ignored_m_Group>; def mlong_calls : Flag<["-"], "mlong-calls">, Group<m_Group>, HelpText<"Generate branches with extended addressability, usually via indirect jumps.">; -} // let Flags = [TargetSpecific] def mdouble_EQ : Joined<["-"], "mdouble=">, Group<m_Group>, MetaVarName<"<n">, Values<"32,64">, Flags<[CC1Option]>, HelpText<"Force double to be <n> bits">, MarshallingInfoInt<LangOpts<"DoubleSize">, "0">; +def LongDouble_Group : OptionGroup<"<LongDouble group>">, Group<m_Group>, + DocName<"Long double flags">, + DocBrief<[{Selects the long double implementation}]>; def mlong_double_64 : Flag<["-"], "mlong-double-64">, Group<LongDouble_Group>, Flags<[CC1Option]>, HelpText<"Force long double to be 64 bits">; def mlong_double_80 : Flag<["-"], "mlong-double-80">, Group<LongDouble_Group>, Flags<[CC1Option]>, HelpText<"Force long double to be 80 bits, padded to 128 bits for storage">; def mlong_double_128 : Flag<["-"], "mlong-double-128">, Group<LongDouble_Group>, Flags<[CC1Option]>, HelpText<"Force long double to be 128 bits">; -let Flags = [TargetSpecific] in { def mno_long_calls : Flag<["-"], "mno-long-calls">, Group<m_Group>, HelpText<"Restore the default behaviour of not generating long calls">; -} // let Flags = [TargetSpecific] def mexecute_only : Flag<["-"], "mexecute-only">, Group<m_arm_Features_Group>, HelpText<"Disallow generation of data access to code sections (ARM only)">; def mno_execute_only : Flag<["-"], "mno-execute-only">, Group<m_arm_Features_Group>, HelpText<"Allow generation of data access to code sections (ARM only)">; -let Flags = [TargetSpecific] in { def mtp_mode_EQ : Joined<["-"], "mtp=">, Group<m_arm_Features_Group>, Values<"soft,cp15,el0,el1,el2,el3">, HelpText<"Thread pointer access method (AArch32/AArch64 only)">; def mpure_code : Flag<["-"], "mpure-code">, Alias<mexecute_only>; // Alias for GCC compatibility @@ -3556,7 +3549,6 @@ def mappletvsimulator_version_min_EQ : Joined<["-"], "mappletvsimulator-version- def mwatchos_version_min_EQ : Joined<["-"], "mwatchos-version-min=">, Group<m_Group>; def mwatchos_simulator_version_min_EQ : Joined<["-"], "mwatchos-simulator-version-min=">, Group<m_Group>; def mwatchsimulator_version_min_EQ : Joined<["-"], "mwatchsimulator-version-min=">, Alias<mwatchos_simulator_version_min_EQ>; -} // let Flags = [TargetSpecific] def march_EQ : Joined<["-"], "march=">, Group<m_Group>, Flags<[CoreOption,TargetSpecific]>, HelpText<"For a list of available architectures for the target use '-mcpu=help'">; def masm_EQ : Joined<["-"], "masm=">, Group<m_Group>, Flags<[NoXarchOption]>; @@ -3573,9 +3565,7 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">, Group<m_Group>, Flags<[NoXarchOp def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group<m_Group>; def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">, Group<m_Group>; def mno_default_build_attributes : Joined<["-"], "mno-default-build-attributes">, Group<m_Group>; -let Flags = [TargetSpecific] in { def mconstant_cfstrings : Flag<["-"], "mconstant-cfstrings">, Group<clang_ignored_m_Group>; -} // let Flags = [TargetSpecific] def mconsole : Joined<["-"], "mconsole">, Group<m_Group>, Flags<[NoXarchOption]>; def mwindows : Joined<["-"], "mwindows">, Group<m_Group>, Flags<[NoXarchOption]>; def mdll : Joined<["-"], "mdll">, Group<m_Group>, Flags<[NoXarchOption]>; @@ -3584,8 +3574,7 @@ def mthreads : Joined<["-"], "mthreads">, Group<m_Group>, Flags<[NoXarchOption]> def mguard_EQ : Joined<["-"], "mguard=">, Group<m_Group>, Flags<[NoXarchOption]>, HelpText<"Enable or disable Control Flow Guard checks and guard tables emission">, Values<"none,cf,cf-nochecks">; -let Flags = [TargetSpecific] in { -def mcpu_EQ : Joined<["-"], "mcpu=">, Group<m_Group>, +def mcpu_EQ : Joined<["-"], "mcpu=">, Group<m_Group>, TargetSpecific, HelpText<"For a list of available CPUs for the target use '-mcpu=help'">; def mmcu_EQ : Joined<["-"], "mmcu=">, Group<m_Group>; def msim : Flag<["-"], "msim">, Group<m_Group>; @@ -3594,22 +3583,16 @@ def mfix_and_continue : Flag<["-"], "mfix-and-continue">, Group<clang_ignored_m_ def mieee_fp : Flag<["-"], "mieee-fp">, Group<clang_ignored_m_Group>; def minline_all_stringops : Flag<["-"], "minline-all-stringops">, Group<clang_ignored_m_Group>; def mno_inline_all_stringops : Flag<["-"], "mno-inline-all-stringops">, Group<clang_ignored_m_Group>; -} // let Flags = [TargetSpecific] def malign_double : Flag<["-"], "malign-double">, Group<m_Group>, Flags<[CC1Option]>, HelpText<"Align doubles to two words in structs (x86 only)">, MarshallingInfoFlag<LangOpts<"AlignDouble">>; -let Flags = [TargetSpecific] in { def mfloat_abi_EQ : Joined<["-"], "mfloat-abi=">, Group<m_Group>, Values<"soft,softfp,hard">; def mfpmath_EQ : Joined<["-"], "mfpmath=">, Group<m_Group>; -} // let Flags = [TargetSpecific] def mfpu_EQ : Joined<["-"], "mfpu=">, Group<m_Group>; -let Flags = [TargetSpecific] in { def mhwdiv_EQ : Joined<["-"], "mhwdiv=">, Group<m_Group>; def mhwmult_EQ : Joined<["-"], "mhwmult=">, Group<m_Group>; -} // let Flags = [TargetSpecific] def mglobal_merge : Flag<["-"], "mglobal-merge">, Group<m_Group>, Flags<[CC1Option]>, HelpText<"Enable merging of globals">; -let Flags = [TargetSpecific] in { def mhard_float : Flag<["-"], "mhard-float">, Group<m_Group>; def mios_version_min_EQ : Joined<["-"], "mios-version-min=">, Group<m_Group>, HelpText<"Set iOS deployment target">; @@ -3618,8 +3601,8 @@ def : Joined<["-"], "miphoneos-version-min=">, def mios_simulator_version_min_EQ : Joined<["-"], "mios-simulator-version-min=">, Group<m_Group>; def : Joined<["-"], "miphonesimulator-version-min=">, Alias<mios_simulator_version_min_EQ>; def mkernel : Flag<["-"], "mkernel">, Group<m_Group>; -def mlinker_version_EQ : Joined<["-"], "mlinker-version=">, Group<m_Group>, Flags<[NoXarchOption]>; -} // let Flags = [TargetSpecific] +def mlinker_version_EQ : Joined<["-"], "mlinker-version=">, Group<m_Group>, + Flags<[NoXarchOption]>; def mllvm : Separate<["-"], "mllvm">,Flags<[CC1Option,CC1AsOption,CoreOption,FC1Option,FlangOption]>, HelpText<"Additional arguments to forward to LLVM's option processing">, MarshallingInfoStringVector<FrontendOpts<"LLVMArgs">>; @@ -3683,11 +3666,9 @@ def mno_tls_direct_seg_refs : Flag<["-"], "mno-tls-direct-seg-refs">, Group<m_Gr HelpText<"Disable direct TLS access through segment registers">, MarshallingInfoFlag<CodeGenOpts<"IndirectTlsSegRefs">>; def mno_relax_all : Flag<["-"], "mno-relax-all">, Group<m_Group>; -let Flags = [TargetSpecific] in { def mno_rtd: Flag<["-"], "mno-rtd">, Group<m_Group>; def mno_soft_float : Flag<["-"], "mno-soft-float">, Group<m_Group>; def mno_stackrealign : Flag<["-"], "mno-stackrealign">, Group<m_Group>; -} // let Flags = [TargetSpecific] def mretpoline : Flag<["-"], "mretpoline">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>; def mno_retpoline : Flag<["-"], "mno-retpoline">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>; @@ -3716,19 +3697,16 @@ def mno_relax : Flag<["-"], "mno-relax">, Group<m_Group>, def msmall_data_limit_EQ : Joined<["-"], "msmall-data-limit=">, Group<m_Group>, Alias<G>, HelpText<"Put global and static data smaller than the limit into a special section">; -let Flags = [TargetSpecific] in { def msave_restore : Flag<["-"], "msave-restore">, Group<m_riscv_Features_Group>, HelpText<"Enable using library calls for save and restore">; def mno_save_restore : Flag<["-"], "mno-save-restore">, Group<m_riscv_Features_Group>, HelpText<"Disable using library calls for save and restore">; -} // let Flags = [TargetSpecific] def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, Group<m_Group>, Flags<[CC1Option]>, Alias<mcmodel_EQ>, AliasArgs<["small"]>, HelpText<"Equivalent to -mcmodel=small, compatible with RISC-V gcc.">; def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, Group<m_Group>, Flags<[CC1Option]>, Alias<mcmodel_EQ>, AliasArgs<["medium"]>, HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">; -let Flags = [TargetSpecific] in { def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>, HelpText<"Enable use of experimental RISC-V extensions.">; def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>, @@ -3742,12 +3720,10 @@ def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>, HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch only)">; def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>, HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch only)">; -} // let Flags = [TargetSpecific] def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>, HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">; def mno_strict_align : Flag<["-"], "mno-strict-align">, Alias<munaligned_access>, Flags<[CC1Option,HelpHidden]>, HelpText<"Allow memory accesses to be unaligned (same as munaligned-access)">; -let Flags = [TargetSpecific] in { def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>; def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>, HelpText<"Disallow generation of complex IT blocks.">; @@ -3764,7 +3740,6 @@ def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>, HelpText<"Disallow use of CRC instructions (ARM only)">; def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_Group>, HelpText<"Disallow converting instructions with negative immediates to their negation or inversion.">; -} // let Flags = [TargetSpecific] def mcmse : Flag<["-"], "mcmse">, Group<m_arm_Features_Group>, Flags<[NoXarchOption,CC1Option]>, HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">, @@ -3779,7 +3754,6 @@ defm aapcs_bitfield_width : BoolOption<"f", "aapcs-bitfield-width", BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement stating that" " volatile bit-field width is dictated by the field container type. (ARM only).">>, Group<m_arm_Features_Group>; -let Flags = [TargetSpecific] in { def mframe_chain : Joined<["-"], "mframe-chain=">, Group<m_arm_Features_Group>, Values<"none,aapcs,aapcs+leaf">, HelpText<"Select the frame chain model used to emit frame records (Arm only).">; @@ -3830,7 +3804,6 @@ foreach i = {8-15,18} in def msve_vector_bits_EQ : Joined<["-"], "msve-vector-bits=">, Group<m_aarch64_Features_Group>, HelpText<"Specify the size in bits of an SVE vector register. Defaults to the" " vector length agnostic value of \"scalable\". (AArch64 only)">; -} // let Flags = [TargetSpecific] def mvscale_min_EQ : Joined<["-"], "mvscale-min=">, Group<m_aarch64_Features_Group>, Flags<[NoXarchOption,CC1Option]>, @@ -3845,7 +3818,6 @@ def mvscale_max_EQ : Joined<["-"], "mvscale-max=">, def msign_return_address_EQ : Joined<["-"], "msign-return-address=">, Flags<[CC1Option]>, Group<m_Group>, Values<"none,all,non-leaf">, HelpText<"Select return address signing scope">; -let Flags = [TargetSpecific] in { def mbranch_protection_EQ : Joined<["-"], "mbranch-protection=">, Group<m_Group>, HelpText<"Enforce targets of indirect branches and function returns">; @@ -3883,7 +3855,6 @@ def mno_extended_const : Flag<["-"], "mno-extended-const">, Group<m_wasm_Feature def mexec_model_EQ : Joined<["-"], "mexec-model=">, Group<m_wasm_Features_Driver_Group>, Values<"command,reactor">, HelpText<"Execution model (WebAssembly only)">; -} // let Flags = [TargetSpecific] defm amdgpu_ieee : BoolOption<"m", "amdgpu-ieee", CodeGenOpts<"EmitIEEENaNCompliantInsts">, DefaultTrue, @@ -3917,7 +3888,6 @@ defm unsafe_fp_atomics : BoolOption<"m", "unsafe-fp-atomics", def faltivec : Flag<["-"], "faltivec">, Group<f_Group>, Flags<[NoXarchOption]>; def fno_altivec : Flag<["-"], "fno-altivec">, Group<f_Group>, Flags<[NoXarchOption]>; -let Flags = [TargetSpecific] in { def maltivec : Flag<["-"], "maltivec">, Group<m_ppc_Features_Group>; def mno_altivec : Flag<["-"], "mno-altivec">, Group<m_ppc_Features_Group>; def mpcrel: Flag<["-"], "mpcrel">, Group<m_ppc_Features_Group>; @@ -3927,12 +3897,10 @@ def mno_prefixed: Flag<["-"], "mno-prefixed">, Group<m_ppc_Features_Group>; def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>; def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>; def mefpu2 : Flag<["-"], "mefpu2">, Group<m_ppc_Features_Group>; -} // let Flags = [TargetSpecific] def mabi_EQ_quadword_atomics : Flag<["-"], "mabi=quadword-atomics">, Group<m_Group>, Flags<[CC1Option]>, HelpText<"Enable quadword atomics ABI on AIX (AIX PPC64 only). Uses lqarx/stqcx. instructions.">, MarshallingInfoFlag<LangOpts<"EnableAIXQuadwordAtomicsABI">>; -let Flags = [TargetSpecific] in { def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>; def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>; def msecure_plt : Flag<["-"], "msecure-plt">, Group<m_ppc_Features_Group>; @@ -3995,7 +3963,6 @@ def mrop_protect : Flag<["-"], "mrop-protect">, Group<m_ppc_Features_Group>; def mprivileged : Flag<["-"], "mprivileged">, Group<m_ppc_Features_Group>; -} // let Flags = [TargetSpecific] def maix_struct_return : Flag<["-"], "maix-struct-return">, Group<m_Group>, Flags<[CC1Option]>, HelpText<"Return all structs in memory (PPC32 only)">; @@ -4006,10 +3973,8 @@ def mxcoff_roptr : Flag<["-"], "mxcoff-roptr">, Group<m_Group>, Flags<[CC1Option HelpText<"Place constant objects with relocatable address values in the RO data section and add -bforceimprw to the linker flags (AIX only)">; def mno_xcoff_roptr : Flag<["-"], "mno-xcoff-roptr">, Group<m_Group>, TargetSpecific; -let Flags = [TargetSpecific] in { def mvx : Flag<["-"], "mvx">, Group<m_Group>; def mno_vx : Flag<["-"], "mno-vx">, Group<m_Group>; -} // let Flags = [TargetSpecific] defm zvector : BoolFOption<"zvector", LangOpts<"ZVector">, DefaultFalse, @@ -4098,8 +4063,6 @@ def mpacked_stack : Flag<["-"], "mpacked-stack">, HelpText<"Use packed stack lay Flags<[CC1Option]>, Group<m_Group>, MarshallingInfoFlag<CodeGenOpts<"PackedStack">>; def mno_packed_stack : Flag<["-"], "mno-packed-stack">, Flags<[CC1Option]>, Group<m_Group>; - -let Flags = [TargetSpecific] in { def mips16 : Flag<["-"], "mips16">, Group<m_mips_Features_Group>; def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_mips_Features_Group>; def mmicromips : Flag<["-"], "mmicromips">, Group<m_mips_Features_Group>; @@ -4115,12 +4078,10 @@ def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">, def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, Group<m_mips_Features_Group>; -} // let Flags = [TargetSpecific] def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, IgnoredGCCCompat; def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group<m_Group>, IgnoredGCCCompat; -let Flags = [TargetSpecific] in { def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">, Group<m_mips_Features_Group>, HelpText<"Change indirect jump instructions to inhibit speculation">; @@ -4186,7 +4147,6 @@ def mvirt : Flag<["-"], "mvirt">, Group<m_mips_Features_Group>; def mno_virt : Flag<["-"], "mno-virt">, Group<m_mips_Features_Group>; def mginv : Flag<["-"], "mginv">, Group<m_mips_Features_Group>; def mno_ginv : Flag<["-"], "mno-ginv">, Group<m_mips_Features_Group>; -} // let Flags = [TargetSpecific] def mips1 : Flag<["-"], "mips1">, Alias<march_EQ>, AliasArgs<["mips1"]>, Group<m_mips_Features_Group>, HelpText<"Equivalent to -march=mips1">, Flags<[HelpHidden]>; @@ -4662,7 +4622,6 @@ def _write_user_dependencies : Flag<["--"], "write-user-dependencies">, Alias<MM def _ : Joined<["--"], "">, Flags<[Unsupported]>; // Hexagon feature flags. -let Flags = [TargetSpecific] in { def mieee_rnd_near : Flag<["-"], "mieee-rnd-near">, Group<m_hexagon_Features_Group>; def mv5 : Flag<["-"], "mv5">, Group<m_hexagon_Features_Group>, Alias<mcpu_EQ>, @@ -4716,7 +4675,6 @@ def mno_hexagon_hvx_ieee_fp : Flag<["-"], "mno-hvx-ieee-fp">, HelpText<"Disable Hexagon HVX IEEE floating-point">; def ffixed_r19: Flag<["-"], "ffixed-r19">, Group<f_Group>, HelpText<"Reserve register r19 (Hexagon only)">; -} // let Flags = [TargetSpecific] def mmemops : Flag<["-"], "mmemops">, Group<m_hexagon_Features_Group>, Flags<[CC1Option]>, HelpText<"Enable generation of memop instructions">; def mno_memops : Flag<["-"], "mno-memops">, Group<m_hexagon_Features_Group>, @@ -4737,7 +4695,6 @@ def mcabac: Flag<["-"], "mcabac">, Group<m_hexagon_Features_Group>, HelpText<"Enable CABAC instructions">; // SPARC feature flags -let Flags = [TargetSpecific] in { def mfpu : Flag<["-"], "mfpu">, Group<m_sparc_Features_Group>; def mno_fpu : Flag<["-"], "mno-fpu">, Group<m_sparc_Features_Group>; def mfsmuld : Flag<["-"], "mfsmuld">, Group<m_sparc_Features_Group>; @@ -4752,10 +4709,8 @@ def mvis3 : Flag<["-"], "mvis3">, Group<m_sparc_Features_Group>; def mno_vis3 : Flag<["-"], "mno-vis3">, Group<m_sparc_Features_Group>; def mhard_quad_float : Flag<["-"], "mhard-quad-float">, Group<m_sparc_Features_Group>; def msoft_quad_float : Flag<["-"], "msoft-quad-float">, Group<m_sparc_Features_Group>; -} // let Flags = [TargetSpecific] // M68k features flags -let Flags = [TargetSpecific] in { def m68000 : Flag<["-"], "m68000">, Group<m_m68k_Features_Group>; def m68010 : Flag<["-"], "m68010">, Group<m_m68k_Features_Group>; def m68020 : Flag<["-"], "m68020">, Group<m_m68k_Features_Group>; @@ -4771,10 +4726,8 @@ foreach i = {0-6} in foreach i = {0-7} in def ffixed_d#i : Flag<["-"], "ffixed-d"#i>, Group<m_m68k_Features_Group>, HelpText<"Reserve the d"#i#" register (M68k only)">; -} // let Flags = [TargetSpecific] // X86 feature flags -let Flags = [TargetSpecific] in { def mx87 : Flag<["-"], "mx87">, Group<m_x86_Features_Group>; def mno_x87 : Flag<["-"], "mno-x87">, Group<m_x86_Features_Group>; def m80387 : Flag<["-"], "m80387">, Alias<mx87>; @@ -4981,7 +4934,6 @@ def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group< def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; def mvzeroupper : Flag<["-"], "mvzeroupper">, Group<m_x86_Features_Group>; def mno_vzeroupper : Flag<["-"], "mno-vzeroupper">, Group<m_x86_Features_Group>; -} // let Flags = [TargetSpecific] // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag diff --git a/clang/test/Driver/munaligned-access-unused.c b/clang/test/Driver/munaligned-access-unused.c index 958a611a1819e..1654692dfd1c4 100644 --- a/clang/test/Driver/munaligned-access-unused.c +++ b/clang/test/Driver/munaligned-access-unused.c @@ -5,4 +5,4 @@ // RUN: %clang --target=x86_64 -mstrict-align -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=strict-align // RUN: %clang --target=x86_64 -mno-strict-align -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=no-strict-align -// CHECK: error: unsupported option '-m{{(no-)?}}unaligned-access' for target '{{.*}}' +// CHECK: clang: warning: argument unused during compilation: '-m[[OPTION]]' [-Wunused-command-line-argument] diff --git a/clang/test/Driver/x86-malign-branch.c b/clang/test/Driver/x86-malign-branch.c index a72125c9b1123..a71b18105baa3 100644 --- a/clang/test/Driver/x86-malign-branch.c +++ b/clang/test/Driver/x86-malign-branch.c @@ -41,4 +41,4 @@ // RUN: %clang -target aarch64 -malign-branch-boundary=7 %s -c -### 2>&1 | FileCheck --check-prefix=UNUSED %s // RUN: %clang -target aarch64 -mpad-max-prefix-size=15 %s -c -### 2>&1 | FileCheck --check-prefix=UNUSED %s // RUN: %clang -target aarch64 -mbranches-within-32B-boundaries %s -c -### 2>&1 | FileCheck --check-prefix=UNUSED %s -// UNUSED: error: unsupported option '{{.*}}' for target '{{.*}}' +// UNUSED: warning: argument unused _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
