Yunzezhu updated this revision to Diff 528698.
Yunzezhu added a comment.
I made the flag isCLZForZeroUndef set to false only when target support
extension zbb or xtheadbb, and this will prevent making codegen worse when
target does not support abb or xtheadbb.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151867/new/
https://reviews.llvm.org/D151867
Files:
clang/lib/Basic/Targets/RISCV.h
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -26,6 +26,32 @@
return __builtin_riscv_orc_b_64(a);
}
+// RV64ZBB-LABEL: @clz_32_generic(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+ return __builtin_clz(a);
+}
+
+// RV64ZBB-LABEL: @clz_64_generic(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT: [[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT: ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+ return __builtin_clzl(a);
+}
+
// RV64ZBB-LABEL: @clz_32(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -50,6 +76,32 @@
return __builtin_riscv_clz_64(a);
}
+// RV64ZBB-LABEL: @ctz_32_generic(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+ return __builtin_ctz(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64_generic(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT: [[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT: ret i64 [[CONV]]
+//
+long ctz_64_generic(long a) {
+ return __builtin_ctzl(a);
+}
+
// RV64ZBB-LABEL: @ctz_32(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -2,6 +2,18 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadbb -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64XTHEADBB
+// RV64XTHEADBB-LABEL: @clz_32_generic(
+// RV64XTHEADBB-NEXT: entry:
+// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64XTHEADBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64XTHEADBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+ return __builtin_clz(a);
+}
+
// RV64XTHEADBB-LABEL: @clz_32(
// RV64XTHEADBB-NEXT: entry:
// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -27,6 +39,20 @@
return __builtin_riscv_clz_32(~a);
}
+// RV64XTHEADBB-LABEL: @clz_64_generic(
+// RV64XTHEADBB-NEXT: entry:
+// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64XTHEADBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64XTHEADBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64XTHEADBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
+// RV64XTHEADBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT: [[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64XTHEADBB-NEXT: ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+ return __builtin_clzl(a);
+}
+
// RV64XTHEADBB-LABEL: @clz_64(
// RV64XTHEADBB-NEXT: entry:
// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -14,6 +14,18 @@
return __builtin_riscv_orc_b_32(a);
}
+// RV32ZBB-LABEL: @clz_32_generic(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+ return __builtin_clz(a);
+}
+
// RV32ZBB-LABEL: @clz_32(
// RV32ZBB-NEXT: entry:
// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -26,6 +38,18 @@
return __builtin_riscv_clz_32(a);
}
+// RV32ZBB-LABEL: @ctz_32_generic(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+ return __builtin_ctz(a);
+}
+
// RV32ZBB-LABEL: @ctz_32(
// RV32ZBB-NEXT: entry:
// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
@@ -2,6 +2,18 @@
// RUN: %clang_cc1 -triple riscv32 -target-feature +xtheadbb -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32XTHEADBB
+// RV32XTHEADBB-LABEL: @clz_32_generic(
+// RV32XTHEADBB-NEXT: entry:
+// RV32XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32XTHEADBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32XTHEADBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32XTHEADBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV32XTHEADBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+ return __builtin_clz(a);
+}
+
// RV32XTHEADBB-LABEL: @clz_32(
// RV32XTHEADBB-NEXT: entry:
// RV32XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -14,6 +26,18 @@
return __builtin_riscv_clz_32(a);
}
+// RV32XTHEADBB-LABEL: @ctz_32_generic(
+// RV32XTHEADBB-NEXT: entry:
+// RV32XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32XTHEADBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32XTHEADBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32XTHEADBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV32XTHEADBB-NEXT: ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+ return __builtin_ctz(a);
+}
+
// RV32XTHEADBB-LABEL: @clo_32(
// RV32XTHEADBB-NEXT: entry:
// RV32XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -58,6 +58,12 @@
ArrayRef<Builtin::Info> getTargetBuiltins() const override;
+ bool isCLZForZeroUndef() const override {
+ if (ISAInfo->hasExtension("zbb") || ISAInfo->hasExtension("xtheadbb"))
+ return false;
+ return true;
+ }
+
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::VoidPtrBuiltinVaList;
}
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